Intel Xeon X3470 BX80605X3470 Manual De Usuario
Los códigos de productos
BX80605X3470
Signal Description
48
Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
6.1
System Memory Interface
Table 6-2.
Memory Channel A
Signal Name
Description
Direction
Type
SA_BS[2:0]
Bank Select: These signals define which banks are
selected within each SDRAM rank.
O
DDR3
SA_CAS#
CAS Control Signal: Used with SA_RAS# and SA_WE#
(along with SA_CS#) to define the SDRAM Commands.
O
DDR3
SA_CK#[1:0]
SDRAM Inverted Differential Clock: Channel A SDRAM
Differential clock signal-pair complement.
O
DDR3
SA_CK#[3:2]
SDRAM Inverted Differential Clock: Channel A SDRAM
Differential clock signal-pair complement.
O
DDR3
SA_CK[1:0]
SDRAM Differential Clock: Channel A SDRAM Differential
clock signal pair.
The crossing of the positive edge of SA_CKx and the
The crossing of the positive edge of SA_CKx and the
negative edge of its complement SA_CKx# are used to
sample the command and control signals on the SDRAM.
O
DDR3
SA_CK[3:2]
SDRAM Differential Clock: Channel A SDRAM Differential
clock signal pair.
The crossing of the positive edge of SA_CKx and the
The crossing of the positive edge of SA_CKx and the
negative edge of its complement SA_CKx# are used to
sample the command and control signals on the SDRAM.
O
DDR3
SA_CKE[3:0]
Clock Enable: (1 per rank) used to:
• Initialize the SDRAMs during power-up
• Power-down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh
• Power-down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh
during STR
O
DDR3
SA_CS#[3:0]
Chip Select: (1 per rank) Used to select particular SDRAM
components during the active state. There is one Chip
Select for each SDRAM rank.
O
DDR3
SA_CS#[7:4]
These signals are only used for processors and platforms
that have Registered DIMM support. These signals are
used to select particular SDRAM components during the
active state and SA_CS#[7:6] are used as the on die
termination for the first DIMM.
O
DDR3
SA_DM[7:0]
Data Mask: These signals are used to mask individual
bytes of data in the case of a partial write, and to
interrupt burst writes.
When activated during writes, the corresponding data
When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one
SA_DM[7:0] for every data byte lane.
Note: These signals are not used by the Intel Xeon
Note: These signals are not used by the Intel Xeon
processor 3400 series. They are connected to V
SS
on the
package.
SA_DQ[63:0]
Data Bus: Channel A data signal interface to the SDRAM
data bus.
I/O
DDR3
SA_DQS[8:0]
SA_DQS#[8:0]
Data Strobes: SA_DQS[8:0] and its complement signal
group make up a differential strobe pair. The data is
captured at the crossing point of SA_DQS[8:0] and its
SA_DQS#[8:0] during read and write transactions.
I/O
DDR3
SA_ECC_CB[7:0]
Data Lines for ECC Check Byte.
I/O
DDR3
SA_MA[15:0]
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
O
DDR3
SA_ODT[3:0]
On Die Termination: Active Termination Control
O
DDR3
SA_RAS#
RAS Control Signal: Used with SA_CAS# and SA_WE#
(along with SA_CS#) to define the SRAM Commands.
O
DDR3
SA_WE#
Write Enable Control Signal: Used with SA_RAS# and
SA_CAS# (along with SA_CS#) to define the SDRAM
Commands.
O
DDR3