Cypress CY7C67300 Manual De Usuario
CY7C67300
Document #: 38-08015 Rev. *J
Page 48 of 99
Device n SOF/EOP Count Register [W]
■
Device 1 SOF/EOP Count Register 0xC094
■
Device 2 SOF/EOP Count Register 0xC0B4
Register Description
The Device n SOF/EOP Count register is written with the time
expected between receiving a SOF/EOP. If the SOF/EOP
counter expires before an SOF/EOP is received, an SOF/EOP
Timeout Interrupt can be generated. The SOF/EOP Timeout
Interrupt Enable and SOF/EOP Timeout Interrupt Flag are
located in the Device n Interrupt Enable and Status registers
respectively.
expected between receiving a SOF/EOP. If the SOF/EOP
counter expires before an SOF/EOP is received, an SOF/EOP
Timeout Interrupt can be generated. The SOF/EOP Timeout
Interrupt Enable and SOF/EOP Timeout Interrupt Flag are
located in the Device n Interrupt Enable and Status registers
respectively.
Set the SOF/EOP count slightly greater than the expected
SOF/EOP interval. The SOF/EOP counter decrements at a
12 MHz rate. Therefore, in the case of an expected 1 ms
SOF/EOP interval, the SOF/EOP count is set slightly greater
than 0x2EE0.
SOF/EOP interval. The SOF/EOP counter decrements at a
12 MHz rate. Therefore, in the case of an expected 1 ms
SOF/EOP interval, the SOF/EOP count is set slightly greater
than 0x2EE0.
Count
(Bits [13:0])
The Count field contains the current value of the SOF/EOP down
counter. At power up and reset, this value is set to 0x2EE0 and
for expected 1 ms SOF/EOP intervals, this SOF/EOP count is
increased slightly.
counter. At power up and reset, this value is set to 0x2EE0 and
for expected 1 ms SOF/EOP intervals, this SOF/EOP count is
increased slightly.
Reserved
Write all reserved bits with ’0’.
OTG Control Registers
There is one register dedicated for On-The-Go operation. This
register is covered in this section and summarized in
register is covered in this section and summarized in
.
OTG Control Register [0xC098] [R/W]
Register Description
The OTG Control register allows control and monitoring over the
OTG port on Port1A. Note that the D± pull up and pull down bits
override the setting in the USB 0 Control register for this port.
OTG port on Port1A. Note that the D± pull up and pull down bits
override the setting in the USB 0 Control register for this port.
VBUS Pull-up Enable
(Bit 13)
The VBUS Pull-up Enable bit enables or disables a 500 ohm pull
up resistor onto OTG VBus.
up resistor onto OTG VBus.
1:
500 ohm pull up resistor enabled
0:
500 ohm pull up resistor disabled
Table 73. Device n SOF/EOP Count Register
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
Count...
Read/Write
-
-
R
R
R
R
R
R
Default
0
0
1
0
1
1
1
0
Bit #
7
6
5
4
3
2
1
0
Field
...Count
Read/Write
R
R
R
R
R
R
R
R
Default
1
1
1
0
0
0
0
0
Table 74. OTG Register
Register Name
Address
R/W
OTG Control Register
C098H
R/W
Table 75. OTG Control Register
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
VBUS
Pull-up Enable
Receive
Disable
Charge Pump
Enable
VBUS
Discharge Enable
D+
Pull-up Enable
D–
Pull-up Enable
Read/Write
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
D+
Pull-down Enable
D–
Pull-down Enable
Reserved
OTG Data
Status
ID
Status
VBUS Valid
Flag
Read/Write
R/W
R/W
-
-
-
R
R
R
Default
0
0
0
0
0
X
X
X