Cypress CY7C67300 Manual De Usuario
CY7C67300
Document #: 38-08015 Rev. *J
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Interrupt 0 Polarity Select
(Bit 1)
The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.
1:
1:
Sets IRQ0 to rising edge
0:
Sets IRQ0 to falling edge
Interrupt 0 Enable
(Bit 0)
The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO
bit on the interrupt Enable register must also be set in order for
this for this interrupt to be enabled.
1:
bit on the interrupt Enable register must also be set in order for
this for this interrupt to be enabled.
1:
Enable IRQ0
0:
Disable IRQ0
Reserved
Write all reserved bits with ’0’.
GPIO n Output Data Register [R/W]
■
GPIO 0 Output Data Register 0xC01E
■
GPIO 1 Output Data Register 0xC024
Register Description
The GPIO n Output Data register controls the output data of the
GPIO pins. The GPIO 0 Output Data register controls GPIO15 to
GPIO0 while the GPIO 1 Output Data register controls GPIO31
to GPIO16. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data
Register).
GPIO pins. The GPIO 0 Output Data register controls GPIO15 to
GPIO0 while the GPIO 1 Output Data register controls GPIO31
to GPIO16. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data
Register).
Data
(Bits [15:0])
The Data field[15:0] writes to the corresponding GPIO 15–0 or
GPIO31–16 pins as output data.
GPIO31–16 pins as output data.
GPIO n Input Data Register [R]
■
GPIO 0 Input Data Register 0xC020
■
GPIO 1 Input Data Register 0xC026
Register Description
The GPIO n Input Data register reads the input data of the GPIO
pins. The GPIO 0 Input Data register reads from GPIO15 to
GPIO0 while the GPIO 1 Input Data register reads from GPIO31
to GPIO16.
pins. The GPIO 0 Input Data register reads from GPIO15 to
GPIO0 while the GPIO 1 Input Data register reads from GPIO31
to GPIO16.
Data
(Bits [15:0])
The Data field[15:0] contains the voltage values on the corre-
sponding GPIO15–0 or GPIO31–16 input pins.
sponding GPIO15–0 or GPIO31–16 input pins.
Table 79. GPIO n Output Data Register
Bit #
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
Field
Data...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
Field
...Data
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Table 80. GPIO n Input Data Register
Bit #
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
Field
Data...
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit #
23/7
22/6
21//5
20/4
19/3
18/2
17/1
16/0
Field
...Data
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0