Cypress CY7C67300 Manual De Usuario

Document #: 38-08015 Rev. *J

Page 57 of 99

 (Bit 4)

The Transmit Ready bit is a read only bit that indicates if the HSS
Transmit FIFO is ready for the CPU to load new data for trans-
mission.

 HSS transmit FIFO ready for loading

 HSS transmit FIFO not ready for loading

(Bit 3)

The Packet Mode Select bit selects between Receive Packet
Ready and Receive Ready as the interrupt source for the RxIntr
interrupt.

 Selects Receive Packet Ready as the source

 Selects Receive Ready as the source

 (Bit 2)

The Receive Overflow Flag bit indicates if the Receive FIFO
overflowed when set. This flag can be cleared by writing a ‘1’ to
this bit.

 Overflow occurred

 Overflow did not occur

 (Bit 1)

The Receive Packet Ready Flag bit is a read only bit that
indicates if the HSS receive FIFO is full with eight bytes or not.

 HSS receive FIFO is full 

 HSS receive FIFO is not full

 (Bit 0)

The Receive Ready Flag is a read only bit that indicates if the
HSS receive FIFO is empty or not.

 HSS receive FIFO is not empty (one or more bytes is reading

for reading)

 HSS receive FIFO is empty

The HSS Baud Rate register sets the HSS Baud Rate. At reset,
the default value is 0x0017 which sets the baud rate to 2.0 MHz.

 (Bits [12:0])

The Baud field is the baud rate divisor minus one, in units of 1/48
MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts
a constraint on the Baud Value as follows: 
(24 – 1) 

≤ Baud ≥ (5000 – 1)

Write all reserved bits with ’0’.

Reserved

Baud...

-

-

-

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0

...Baud

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

1

0

1

1

1