Cypress CY7C67300 Manual De Usuario
CY7C67300
Document #: 38-08015 Rev. *J
Page 63 of 99
SIEXmsg Register [W]
■
SIE1msg Register 0x0144
■
SIE2msg Register 0x0148
Register Description
The SIEXmsg register allows an interrupt to be generated on the
HPI port. Any write to this register causes the SIEXmsg flag in
the HPI Status Port to go high and also causes an interrupt on
the HPI_INTR pin. The SIEXmsg flag is automatically cleared
when the HPI port reads from this register.
HPI port. Any write to this register causes the SIEXmsg flag in
the HPI Status Port to go high and also causes an interrupt on
the HPI_INTR pin. The SIEXmsg flag is automatically cleared
when the HPI port reads from this register.
Data
(Bits [15:0])
The Data field[15:0] simply needs to have any value written to it
to cause SIExmsg flag in the HPI Status Port to go high.
to cause SIExmsg flag in the HPI Status Port to go high.
HPI Mailbox Register [0xC0C6] [R/W]
Register Description
The HPI Mailbox register provides a common mailbox between
the CY7C67300 and the external host processor.
the CY7C67300 and the external host processor.
If enabled, the HPI Mailbox RX Full interrupt triggers when the
external host processor writes to this register. When the
CY7C67300 reads this register the HPI Mailbox RX Full interrupt
is automatically cleared.
external host processor writes to this register. When the
CY7C67300 reads this register the HPI Mailbox RX Full interrupt
is automatically cleared.
If enabled, the HPI Mailbox TX Empty interrupt triggers when the
external host processor reads from this register. The HPI Mailbox
TX Empty interrupt automatically clears when the CY7C67300
writes to this register.
external host processor reads from this register. The HPI Mailbox
TX Empty interrupt automatically clears when the CY7C67300
writes to this register.
In addition, when the CY7C67300 writes to this register, the
HPI_INTR signal on the HPI port asserts, signaling the external
processor that there is data in the mailbox to read. The
HPI_INTR signal deasserts when the external host processor
reads from this register.
HPI_INTR signal on the HPI port asserts, signaling the external
processor that there is data in the mailbox to read. The
HPI_INTR signal deasserts when the external host processor
reads from this register.
Message
(Bits [15:0])
The Message field contains the message that the host processor
wrote to the HPI Mailbox register.
wrote to the HPI Mailbox register.
Table 101. SIEXmsg Register
Bit #
15
14
13
12
11
10
9
8
Field
Data...
Read/Write
W
W
W
W
W
W
W
W
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
...Data
Read/Write
W
W
W
W
W
W
W
W
Default
X
X
X
X
X
X
X
X
Table 102. HPI Mailbox Register
Bit #
15
14
13
12
11
10
9
8
Field
Message...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Message
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0