Motorola DSP56012 Manual De Usuario

I-6

Motorola

HCSR

Bus Error

Host Busy

 

Host Receive FIFO Full

 

Host Receive FIFO Not Empty

 

Host Receive Overrun Error

 

Host Transmit Data Empty

 

Host Transmit Underrun Error

Receive Interrupt Enable

 

Master Mode

 

Slave Mode

 

SPI Data-To-Clock Timing

 

SPI Data-To-Clock Timing Diagram

 

SPI Mode

 

T0EN (TCS Transmitter 0 Enable)

 

T1EN (TCS Transmitter 1 Enable)

 

T2EN (TCS Transmitter 2 Enable)

 

TCKP (TCS Transmitter Clock Polarity)

 

TCS

 

TDIR (TCS Transmitter Data Shift Direction)

 

TDWE (TCS Transmitter Data Word 

Expansion)

 

Timing Skew

 

TLDE (TCS Transmitter Left Data Empty)

 

TMST (TCS Transmitter Master)

 

Transmit Byte Registers (TXH, TXM, TXL)

 

Transmit Data Register Empty bit (TXDE)

 

Transmit Request Enable bit (TREQ)

 

Transmitter Ready bit (TRDY)

 

TRDE (TCS Transmitter Right Data Empty)

 

TRDY bit

 

TREL (TCS Transmitter Relative Timing)

 

TREQ bit

 

TWL0-TWL1 (TCS Transmitter Word Length 

Control)

 

TX0, TX1 and TX2 (SAI Transmit Data 

Registers)

 

TXDE bit

 

TXH register

 

TXIE (TCS Transmitter Interrupt Enable)

 

TXIL (TCS Transmitter Interrupt Location)

 

TXL register

 

TXM register

 

X Data Memory

 

Y Data Memory