IBM REDP-4285-00 Manual De Usuario
Chapter 1. Understanding the Linux operating system
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Draft Document for Review May 4, 2007 11:35 am
4285ch01.fm
6. A device driver such as SCSI or other device specific drivers will take care of write
operation
7. A disk device firmware do hardware operation like seek head, rotation, data transfer to the
sector on the platter.
1.4.2 Cache
In the past 20 years, the performance improvement of processors has outperformed that of
the other components in a computer system such as processor cache, bus, RAM, disk and so
on. Slower access to memory and disk restricts overall system performance, so system
performance is not be benefited by processor speed improvement. The cache mechanism
resolves this problem by caching frequently used data in faster memory. It reduces the
chances of having to access slower memory. Current computer system uses this technique in
most all I/O components such as hard disk drive cache, disk controller cache, file system
cache, cache handled by each application and so on.
the other components in a computer system such as processor cache, bus, RAM, disk and so
on. Slower access to memory and disk restricts overall system performance, so system
performance is not be benefited by processor speed improvement. The cache mechanism
resolves this problem by caching frequently used data in faster memory. It reduces the
chances of having to access slower memory. Current computer system uses this technique in
most all I/O components such as hard disk drive cache, disk controller cache, file system
cache, cache handled by each application and so on.
Memory hierarchy
Figure 1-19 shows the concept of memory hierarchy. As the difference of access speed
between the CPU register and disk is large, the CPU will spend much time waiting for data
from slow disk devices, and therefore it significantly reduces the advantage of a fast CPU.
Memory hierarchal structure reduces this mismatch by placing L1 cache, L2 cache, RAM and
some other caches between the CPU and disk. It enables a process to get less chance to
access slower memory and disk. The memory closer to processor has higher speed and less
size.
between the CPU register and disk is large, the CPU will spend much time waiting for data
from slow disk devices, and therefore it significantly reduces the advantage of a fast CPU.
Memory hierarchal structure reduces this mismatch by placing L1 cache, L2 cache, RAM and
some other caches between the CPU and disk. It enables a process to get less chance to
access slower memory and disk. The memory closer to processor has higher speed and less
size.
This technique can also take advantage of locality of reference principal. The higher cache hit
rate on faster memory is, the faster the access to data is.
rate on faster memory is, the faster the access to data is.
Figure 1-19 Memory hierarchy
Locality of reference
As we stated previously in “Memory hierarchy” above, achieving higher cache hit rate is the
key for performance improvement. To achieve higher cache hit rate, the technique called
“locality of reference” is used. This technique is based on the following principals:
key for performance improvement. To achieve higher cache hit rate, the technique called
“locality of reference” is used. This technique is based on the following principals:
The data most recently used has a high probability of being used in near future (temporal
locality)
locality)
The data resides close to the data which has been used has a high probability of being
used (spatial locality)
used (spatial locality)
Figure 1-20 on page 22 illustrates this principal.
CPU register
CPU
cache
register
RAM
very fast
very slow
Large
speed mismatch
speed mismatch
very fast
fast
Disk
slow
very slow
Disk