Renesas HD74LV2GT04A Manual De Usuario
Rev.2.00, Oct.14.2003, page 1 of 7
HD74LV2GT04A
Triple Inverters / CMOS Logic Level Shifter
REJ03D0139–0200Z
(Previous ADE-205-664A (Z))
Rev.2.00
Oct.14.2003
Description
The HD74LV2GT04A has triple inverters in an 8 pin package. The input protection circuitry on this device
allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while
operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for the
battery powered products (e.g., notebook computers), and the low power consumption extends the battery
life.
allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while
operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for the
battery powered products (e.g., notebook computers), and the low power consumption extends the battery
life.
Features
•
The basic gate function is lined up as Renesas uni logic series.
•
Supplied on emboss taping for high-speed automatic mounting.
•
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
Operating temperature range : –40 to +85°C
•
Logic-level translate function
3.0 V CMOS logic
→
5.0 V CMOS logic (@V
CC
= 5.0 V)
1.8 V or 2.5 V CMOS logic
→
3.3 V CMOS logic (@V
CC
= 3.3 V)
•
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
•
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
•
All the logical input has hysteresis voltage for the slow transition.
•
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Abbreviation
Taping Abbreviation
(Quantity)
(Quantity)
HD74LV2GT04AUSE SSOP-8 pin
TTP-8DBV
US
E (3,000 pcs/reel)