Compaq EV67 Manual De Usuario
2–38
Internal Architecture
Alpha 21264/EV67 Hardware Reference Manual
AMASK and IMPLVER Instruction Values
2.15 AMASK and IMPLVER Instruction Values
The AMASK and IMPLVER instructions return processor type and supported architec-
ture extensions, respectively.
ture extensions, respectively.
2.15.1 AMASK
The 21264/EV67 returns the AMASK instruction values provided in Table 2–15. The
I_CTL register reports the 21264/EV67 pass level (see I_CTL[CHIP_ID], Section
5.2.15).
I_CTL register reports the 21264/EV67 pass level (see I_CTL[CHIP_ID], Section
5.2.15).
The AMASK bit definitions provided in Table 2–15 are defined in Table 2–16.
2.15.2 IMPLVER
For the 21264/EV67, the IMPLVER instruction returns the value 2.
DNZ
[48]
RW
Denormal operands to zero. If this bit is set, treat all Denormal operands as a
signed zero value with the same sign as the Denormal operand.
signed zero value with the same sign as the Denormal operand.
Reserved
[47:0]
1
—
—
1
Alpha architecture FPCR bit 47 (DNOD) is not implemented by the 21264/EV67.
Table 2–15 21264/EV67 AMASK Values
21264/EV67 Pass Level
AMASK Feature Mask Value
See I_CTL[CHIP_ID], Table 5–11
307
16
Table 2–16 AMASK Bit Assignments
Bit
Meaning
0
Support for the byte/word extension (BWX)
The instructions that comprise the BWX extension are LDBU, LDWU, SEXTB,
SEXTW, STB, and STW.
The instructions that comprise the BWX extension are LDBU, LDWU, SEXTB,
SEXTW, STB, and STW.
1
Support for the square-root and floating-point convert extension (FIX)
The instructions that comprise the FIX extension are FTOIS, FTOIT, ITOFF, ITOFS,
ITOFT, SQRTF, SQRTG, SQRTS, and SQRTT.
The instructions that comprise the FIX extension are FTOIS, FTOIT, ITOFF, ITOFS,
ITOFT, SQRTF, SQRTG, SQRTS, and SQRTT.
2
Support for the count extension (CIX)
The instructions that comprise the CIX extension are CTLZ, CTPOP, and CTTZ.
The instructions that comprise the CIX extension are CTLZ, CTPOP, and CTTZ.
8
Support for the multimedia extension (MVI)
The instructions that comprise the MVI extension are MAXSB8, MAXSW4,
MAXUB8, MAXUW4, MINSB8, MINSW4, MINUB8, MINUW4, PERR, PKLB,
PKWB, UNPKBL, and UNPKBW.
The instructions that comprise the MVI extension are MAXSB8, MAXSW4,
MAXUB8, MAXUW4, MINSB8, MINSW4, MINUB8, MINUW4, PERR, PKLB,
PKWB, UNPKBL, and UNPKBW.
9
Support for precise arithmetic trap reporting in hardware. The trap PC is the same as
the instruction PC after the trapping instruction is executed.
the instruction PC after the trapping instruction is executed.
Table 2–14 Floating-Point Control Register Fields (Continued)
Name
Extent
Type
Description