Cypress STK17TA8 Manual De Usuario
STK17TA8
Document #: 001-52039 Rev. **
Page 7 of 23
SRAM WRITE Cycles #1 and #2
Figure 7. SRAM WRITE Cycle #1: W Controlled
Figure 8. SRAM WRITE Cycle #2: E Controlled
Notes
7. If W is low when E goes low, the outputs remain in the high-impedance state.
8.
8.
E or W must be
≥ V
IH
during address transitions.
NO.
Symbols
Parameter
STK17TA8-25
STK17TA8-45
Units
#1
#2
Alt.
Min
Max
Min
Max
11
t
AVAV
t
AVAV
t
WC
Write Cycle Time
25
45
ns
13
t
WLWH
t
WLEH
t
WP
Write Pulse Width
20
30
ns
14
t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write
20
30
ns
15
t
DVWH
t
DVEH
t
DW
Data Set-up to End of Write
10
15
ns
16
t
WHDX
t
EHDX
t
DH
Data Hold after End of Write
0
0
ns
17
t
AVWH
t
AVEH
t
AW
Address Set-up to End of Write
20
30
ns
18
t
AVWL
t
AVEL
t
AS
Address Set-up to Start of Write
0
0
ns
19
t
WHAX
t
EHAX
t
WR
Address Hold after End of Write
0
0
ns
20
t
WLQZ
t
WZ
Write Enable to Output Disable
10
15
ns
21
t
WHQX
t
OW
Output Active after End of Write
3
3
ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
t
AVAV
W
t
WHDX
DATA IN
t
WHAX
t
WLWH
t
AVWL
t
AVWH
DATA VALID
t
WLQZ
t
DVWH
HIGH IMPEDANCE
t
WHQX
t
ELWH
DATA IN
t
AVAV
t
EHDX
t
WLEH
t
EHAX
t
AVEL
t
AVEH
DATA VALID
t
DVEH
HIGH IMPEDANCE
t
ELEH
DATA OUT
E
ADDRESS
W
DATA IN