Cypress CY7C1165V18 Manual De Usuario
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
CY7C1163V18, CY7C1165V18
Document Number: 001-06582 Rev. *D
Page 14 of 29
IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power up or whenever
the TAP controller is given a test logic reset state.
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power up or whenever
the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is given
during the Update IR state.
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is given
during the Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruc-
tion register and the TAP controller is in the Capture-DR state, a
snapshot of data on the inputs and output pins is captured in the
boundary scan register.
the SAMPLE/PRELOAD instructions are loaded into the instruc-
tion register and the TAP controller is in the Capture-DR state, a
snapshot of data on the inputs and output pins is captured in the
boundary scan register.
The user must be aware that the TAP controller clock only oper-
ates at a frequency up to 20 MHz, while the SRAM clock oper-
ates more than an order of magnitude faster. Because there is a
large difference in the clock frequencies, it is possible that during
the Capture-DR state, an input or output undergoes a transition.
The TAP then tries to capture a signal while in transition (meta-
stable state). This does not harm the device but there is no guar-
antee as to the value that is captured. Repeatable results are not
possible.
ates at a frequency up to 20 MHz, while the SRAM clock oper-
ates more than an order of magnitude faster. Because there is a
large difference in the clock frequencies, it is possible that during
the Capture-DR state, an input or output undergoes a transition.
The TAP then tries to capture a signal while in transition (meta-
stable state). This does not harm the device but there is no guar-
antee as to the value that is captured. Repeatable results are not
possible.
To guarantee that the boundary scan register captures the cor-
rect value of a signal, the SRAM signal is stabilized long enough
to meet the TAP controller's capture setup plus hold times (t
rect value of a signal, the SRAM signal is stabilized long enough
to meet the TAP controller's capture setup plus hold times (t
CS
and t
CH
). The SRAM clock input is not captured correctly if there
is no way in a design to stop (or slow) the clock during a SAM-
PLE/PRELOAD instruction. If this is an issue, it is still possible to
capture all other signals and simply ignore the value of the CK
and CK captured in the boundary scan register.
PLE/PRELOAD instruction. If this is an issue, it is still possible to
capture all other signals and simply ignore the value of the CK
and CK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
before the selection of another boundary scan test operation.
latched parallel outputs of the boundary scan register cells
before the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data is shifted in.
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller puts the
output bus into a tri-state mode.
output bus into a tri-state mode.
The boundary scan register has a special bit located at bit 47.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up, and also when the TAP controller
is in the Test Logic Reset state.
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up, and also when the TAP controller
is in the Test Logic Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
future use. Do not use these instructions.