Philips P89LPC902 Manual De Usuario
Philips Semiconductors
User’s Manual - Preliminary -
P89LPC901/902/903
ANALOG COMPARATORS
75
10. ANALOG COMPARATORS
One analog comparator is provided on the P89LPC901 and two analog comparators are provided on both the P89LPC902 and
P89LPC903 . Comparator operation is such that the output is a logical one when the positive input is greater than the negative
input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. The output may be read in a register.
On the P89LPC902 the output may also be routed to a pin. The comparator(s) may be configured to cause an interrupt when the
output value changes.
P89LPC903 . Comparator operation is such that the output is a logical one when the positive input is greater than the negative
input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. The output may be read in a register.
On the P89LPC902 the output may also be routed to a pin. The comparator(s) may be configured to cause an interrupt when the
output value changes.
The connections to the comparator(s) are shown in Figure 10-2 - Figure 10-4. The comparator functions to V
DD
= 2.4V.
When the comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10
microseconds. The comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be
cleared before the interrupt is enabled in order to prevent an immediate interrupt service.
microseconds. The comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be
cleared before the interrupt is enabled in order to prevent an immediate interrupt service.
Comparator Configuration
The comparator(s) have a control register(s), CMPn, and is shown in Figure 10-1. The possible configurations for the comparator
are shown in Figure 10-5.
are shown in Figure 10-5.
Figure 10-1: Comparator Control Registers (CMP1 and CMP2)
CMPn
Address: ACh
Address: ACh
Not bit addressable
Reset Source(s): Any reset
Reset Value: xx000000B
BIT
Reset Source(s): Any reset
Reset Value: xx000000B
BIT
SYMBOL
FUNCTION
CMP.7, 6
-
Reserved for future use.
CMP.5
CEn
Comparator enable. When set, the comparator function is enabled. Comparator output is
stable 10 microseconds after CEn is set.
stable 10 microseconds after CEn is set.
CMP.4
-
Reserved for future use.
CMP.3
CNn
Comparator negative input select. When 0, the comparator reference pin CMPREF is
selected as the negative comparator input. When 1, the internal comparator reference,
Vref, is selected as the negative comparator input.
selected as the negative comparator input. When 1, the internal comparator reference,
Vref, is selected as the negative comparator input.
CMP.2
OEn
Output enable. When 1, the comparator output is connected to the CMPn pin if the
comparator is enabled (CEn = 1). This output is asynchronous to the CPU clock.
comparator is enabled (CEn = 1). This output is asynchronous to the CPU clock.
CMP.1
COn
Comparator output, synchronized to the CPU clock to allow reading by software.
CMP.0
CMFn
Comparator interrupt flag. This bit is set by hardware whenever the comparator output
COn changes state. This bit will cause a hardware interrupt if enabled. Cleared by
software.
COn changes state. This bit will cause a hardware interrupt if enabled. Cleared by
software.
7
6
5
4
3
2
1
0
-
-
CEn
-
CNn
OEn
COn
CMFn