Manual De UsuarioTabla de contenidosFeatures1Functional Description1Selection Guide1Logic Block Diagram - CY7C1441AV33 (1M x 36)2Logic Block Diagram - CY7C1443AV33 (2Mx 18)2Logic Block Diagram - CY7C1447AV33 (512K x 72)3Pin Configurations4Pin Definitions7Functional Overview9Single Read Accesses9Single Write Accesses Initiated by ADSP9Single Write Accesses Initiated by ADSC9Burst Sequences9Interleaved Burst Address Table (MODE = Floating or VDD)9Linear Burst Address Table (MODE = GND)9Sleep Mode9ZZ Mode Electrical Characteristics10Truth Table10Partial Truth Table for Read/Write11Truth Table for Read/Write11Function (CY7C1443AV33)[2]11Truth Table for Read/Write11Function (CY7C1447AV33)[2, 8]11IEEE 1149.1 Serial Boundary Scan (JTAG)12Disabling the JTAG Feature12TAP Controller State Diagram12Test Access Port (TAP)12Test Clock (TCK)12Test MODE SELECT (TMS)12Test Data-In (TDI)12Test Data-Out (TDO)12TAP Controller State Diagram12PERFORMING A TAP RESET12TAP REGISTERS12INSTRUCTION REGISTER13BYPASS REGISTER13BOUNDARY SCAN REGISTER13IDENTIFICATION (ID) REGISTER13TAP Instruction Set13OVERVIEW13IDCODE13SAMPLE Z13SAMPLE/PRELOAD13BYPASS13EXTEST14EXTEST OUTPUT BUS TRI-STATE14Reserved14TAP Timing14TAP AC Switching Characteristics153.3V TAP AC Test Conditions163.3V TAP AC Output Load Equivalent162.5V TAP AC Test Conditions162.5V TAP AC Output Load Equivalent16TAP DC Electrical Characteristics And Operating Conditions (0C < TA < +70C; VDD = 3.135V to 3.6V unless otherwise noted)[11]16Identification Register Definitions17Scan Register Sizes17Identification Codes17165-ball FBGA Boundary Scan Order[13,14]18Maximum Ratings19Operating Range19Electrical Characteristics Over the Operating Range[15, 16]19DC Electrical Characteristics Over the Operating Range19Capacitance20Parameter[17]20Thermal Resistance20Switching Characteristics21Timing Diagrams22Ordering Information26Package Diagrams27Document History Page30Tamaño: 900 KBPáginas: 31Language: EnglishManuales abiertas