Manual De UsuarioTabla de contenidosFeatures1Configurations1Functional Description1Logic Block Diagram (CY7C2561KV18)2Logic Block Diagram (CY7C2576KV18)2Logic Block Diagram (CY7C2563KV18)3Logic Block Diagram (CY7C2565KV18)3Pin Configuration4165-Ball FBGA (13 x 15 x 1.4 mm) Pinout4Functional Overview8Read Operations8Write Operations8Byte Write Operations8Concurrent Transactions8Depth Expansion9Programmable Impedance9Echo Clocks9Valid Data Indicator (QVLD)9On-Die Termination (ODT)9PLL9Application Example10IEEE 1149.1 Serial Boundary Scan (JTAG)13Disabling the JTAG Feature13Test Access Port-Test Clock13Test Mode Select (TMS)13Test Data-In (TDI)13Test Data-Out (TDO)13Performing a TAP Reset13TAP Registers13Instruction Register13Bypass Register13Boundary Scan Register13Identification (ID) Register13TAP Instruction Set13IDCODE14SAMPLE Z14SAMPLE/PRELOAD14BYPASS14EXTEST14EXTEST OUTPUT BUS TRI-STATE14Reserved14TAP Electrical Characteristics16TAP AC Switching Characteristics17TAP Timing and Test Conditions17Power Up Sequence in QDR-II+ SRAM20Power Up Sequence20PLL Constraints20Maximum Ratings21Operating Range21Electrical Characteristics21DC Electrical Characteristics21AC Electrical Characteristics22Capacitance22Thermal Resistance22AC Test Loads and Waveforms23Switching Characteristics24Switching Waveforms25Read/Write/Deselect Sequence [32, 33, 34]25Ordering Information26Package Diagram28Document History Page29Sales, Solutions, and Legal Information29Worldwide Sales and Design Support29Products29PSoC Solutions29Tamaño: 800 KBPáginas: 29Language: EnglishManuales abiertas