Manual De UsuarioTabla de contenidosCover1Cautions3Preface5Contents7Figures of Contents15Tables of Contents21Section 1 Overview251.1 Overview251.2 Internal Block Diagram261.3 Pin Arrangement271.4 Pin Functions29Section 2 CPU312.1 Address Space and Memory Map322.2 Register Configuration342.2.1 General Registers352.2.2 Program Counter (PC)362.2.3 Condition-Code Register (CCR)362.3 Data Formats382.3.1 General Register Data Formats382.3.2 Memory Data Formats402.4 Instruction Set412.4.1 Table of Instructions Classified by Function412.4.2 Basic Instruction Formats502.5 Addressing Modesand Effective Address Calculation522.5.1 Addressing Modes522.5.2 Effective Address Calculation542.6 Basic Bus Cycle572.6.1 Access to On-Chip Memory (RAM, ROM)572.6.2 On-Chip Peripheral Modules582.7 CPU States592.8 Usage Notes602.8.1 Notes on Data Access to Empty Areas602.8.2 EEPMOV Instruction602.8.3 Bit Manipulation Instruction60Section 3 Exception Handling673.1 Exception Sources and Vector Address673.2 Register Descriptions693.2.1 Interrupt Edge Select Register 1(IEGR1)693.2.2 Interrupt Edge Select Register 2(IEGR2)703.2.3 Interrupt Enable Register 1(IENR1)713.2.4 Interrupt Flag Register 1(IRR1)723.2.5 Wakeup Interrupt Flag Register(IWPR)733.3 Reset743.4 Interrupt Exception Handling743.4.1 External Interrupts743.4.2 Internal Interrupts753.4.3 Interrupt Handling Sequence763.4.4 Interrupt Response Time773.5 Usage Notes793.5.1 Interrupts after Reset793.5.2 Notes on Stack Area Use793.5.3 Notes on Rewriting Port Mode Registers79Section 4 Address Break814.1 Register Descriptions814.1.1 Address Break Control Register(ABRKCR)824.1.2 Address Break Status Register(ABRKSR)834.1.3 Break Address Registers (BARH, BARL)834.1.4 Break Data Registers (BDRH, BDRL)844.2 Operation84Section 5 Clock Pulse Generators875.1 System Clock Generator875.1.1 Connecting a Crystal Oscillator885.1.2 Connecting a Ceramic Oscillator895.1.3 External Clock Input Method895.2 Subclock Generator895.2.1 Connecting a 32.768-kHz Crystal Oscillator905.2.2 Pin Connection when Not Using Subclock905.3 Prescalers915.3.1 Prescaler S915.3.2 Prescaler W915.4 Usage Notes915.4.1 Note on Oscillators915.4.2 Notes on Board Design92Section 6 Power-down Modes936.1 Register Descriptions936.1.1 System Control Register 1(SYSCR1)946.1.2 System Control Register 2(SYSCR2)966.1.3 Module Standby Control Register 1(MSTCR1)966.2 Mode Transitions and States of the LSI976.2.1 Sleep Mode1006.2.2 Standby Mode1016.2.3 Subsleep Mode1016.2.4 Subactive Mode1026.3 Operating Frequency in the Active Mode1026.4 Direct Transition1026.4.1 Direct Transition from the Active Mode to the Subactive Mode1026.4.2 Direct Transition from the Subactive Mode to the Active Mode1036.5 Module Standby Function103Section 7 ROM1057.1 Block Configuration1057.2 Register Descriptions1067.2.1 Flash Memory Control Register 1 (FLMCR1)1077.2.2 Flash Memory Control Register 2 (FLMCR2)1087.2.3 Erase Block Register 1 (EBR1)1087.2.4 Flash Memory Power Control Register (FLPWCR)1097.2.5 Flash Memory Enable Register (FENR)1097.3 On-Board Programming Modes1107.3.1 Boot Mode1107.3.2 Programming/Erasing in User Program Mode1137.4 Flash Memory Programming/Erasing1147.4.1 Program/Program-Verify1147.4.2 Erase/Erase-Verify1167.4.3 Interrupt Handling when Programming/Erasing Flash Memory1177.5 Program/Erase Protection1197.5.1 Hardware Protection1197.5.2 Software Protection1197.5.3 Error Protection1197.6 Programmer Mode1207.6.1 Socket Adapter1207.6.2 Programmer Mode Commands1207.6.3 Memory Read Mode1227.6.4 Auto-Program Mode1247.6.5 Auto-Erase Mode1267.6.6 Status Read Mode1287.6.7 Status Polling1297.6.8 Programmer Mode Transition Time1307.6.9 Notes on Memory Programming1307.7 Power-Down States for Flash Memory131Section 8 RAM133Section 9 I/O Ports1359.1 Port 11359.1.1 Port Mode Register 1(PMR1)1369.1.2 Port Control Register 1(PCR1)1379.1.3 Port Data Register 1(PDR1)1379.1.4 Port Pull-Up Control Register 1(PUCR1)1389.1.5 Pin Functions1389.2 Port 21409.2.1 Port Control Register 2(PCR2)1409.2.2 Port Data Register 2(PDR2)1419.2.3 Pin Functions1419.3 Port 51429.3.1 Port Mode Register 5(PMR5)1439.3.2 Port Control Register 5(PCR5)1449.3.3 Port Data Register 5(PDR5)1449.3.4 Port Pull-up Control Register 5(PUCR5)1459.3.5 Pin Functions1459.4 Port 71479.4.1 Port Control Register 7(PCR7)1489.4.2 Port Data Register 7(PDR7)1489.4.3 Pin Functions1499.5 Port 81509.5.1 Port Control Register 8(PCR8)1509.5.2 Port Data Register 8(PDR8)1519.5.3 Pin Functions1519.6 Port B1539.6.1 Port Data Register B(PDRB)154Section 10 Timer A15510.1 Features15510.2 Input/Output Pins15610.3 Register Descriptions15610.3.1 Timer Mode Register A(TMA)15710.3.2 Timer Counter A (TCA)15810.4 Operation15810.4.1 Interval Timer Operation15810.4.2 Clock Time Base Operation15810.4.3 Clock Output15810.5 Usage Note159Section 11 Timer V16111.1 Features16111.2 Input/Output Pins16211.3 Register Descriptions16311.3.1 Timer Counter V (TCNTV)16311.3.2 Time Constant Registers A and B (TCORA, TCORB)16311.3.3 Timer Control Register V0(TCRV0)16411.3.4 Timer Control/Status Register V(TCSRV)16611.3.5 Timer Control Register V1(TCRV1)16711.4 Operation16811.4.1 Timer V operation16811.5 Timer V application examples17011.5.1 Pulse Output with Arbitrary Duty Cycle17011.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input17111.6 Usage Notes172Section 12 Timer W17512.1 Features17512.2 Input/Output Pins17712.3 Register Descriptions17812.3.1 Timer Mode Register W(TMRW)17812.3.2 Timer Control Register W(TCRW)18012.3.3 Timer Interrupt Enable Register W(TIERW)18112.3.4 Timer Status Register W(TSRW)18112.3.5 Timer I/O Control Register 0(TIOR0)18312.3.6 Timer I/O Control Register 1(TIOR1)18412.3.7 Timer Counter (TCNT)18512.3.8 General Registers A to D (GRA to GRD)18512.4 Operation18612.4.1 Normal Operation18612.4.2 PWM Operation19012.5 Operation Timing19412.5.1 TCNT Count Timing19412.5.2 Output Compare Timing19412.5.3 Input Capture Timing19512.5.4 Timing of Counter Clearing by Compare Match19612.5.5 Buffer Operation Timing19612.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match19712.5.7 Timing of IMFA to IMFD Setting at Input Capture19812.5.8 Timing of Status Flag Clearing19812.6 Usage Notes199Section 13 Watchdog Timer20113.1 Features20113.2 Register Descriptions20113.2.1 Timer Control/Status Register WD(TCSRWD)20213.2.2 Timer Counter WD(TCWD)20313.2.3 Timer Mode Register WD(TMWD)20313.3 Operation204Section 14 Serial Communication Interface3 (SCI3)20514.1 Features20514.2 Input/Output Pins20714.3 Register Descriptions20714.3.1 Receive Shift Register (RSR)20814.3.2 Receive Data Register (RDR)20814.3.3 Transmit Shift Register (TSR)20814.3.4 Transmit Data Register (TDR)20814.3.5 Serial Mode Register (SMR)20914.3.6 Serial Control Register 3 (SCR3)21014.3.7 Serial Status Register (SSR)21214.3.8 Bit Rate Register (BRR)21414.4 Operation in Asynchronous Mode21914.4.1 Clock21914.4.2 SCI Initialization22014.4.3 Data Transmission22114.4.4 Serial Data Reception22314.5 Operation in Clocked Synchronous Mode22714.5.1 Clock22714.5.2 SCI Initialization22714.5.3 Serial Data Transmission22814.5.4 Serial Data Reception (Clocked Synchronous Mode)23014.5.5 Simultaneous Serial Data Transmission and Reception23214.6 Multiprocessor Communication Function23414.6.1 Multiprocessor Serial Data Transmission23614.6.2 Multiprocessor Serial Data Reception23714.7 Interrupts24114.8 Usage Notes24214.8.1 Break Detection and Processing24214.8.2 Mark State and Break Detection24214.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)24214.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode243Section 15 I2C Bus Interface 2 (IIC2)24515.1 Features24515.2 Input/Output Pins24715.3 Register Descriptions24715.3.1 I2C Bus Control Register 1 (ICCR1)24815.3.2 I2C Bus Control Register 2 (ICCR2)24915.3.3 I2C Bus Mode Register (ICMR)25115.3.4 I2C Bus Interrupt Enable Register (ICIER)25215.3.5 I2C Bus Status Register (ICSR)25415.3.6 Slave Address Register (SAR)25615.3.7 I2C Bus Transmit Data Register (ICDRT)25715.3.8 I2C Bus Receive Data Register (ICDRR)25715.3.9 I2C Bus Shift Register (ICDRS)25715.4 Operation25815.4.1 I2C Bus Format25815.4.2 Master Transmit Operation25915.4.3 Master Receive Operation26115.4.4 Slave Transmit Operation26315.4.5 Slave Receive Operation26515.4.6 Clocked Synchronous Serial Format26715.4.7 Noise Canceler26915.4.8 Example of Use27015.5 Interrupt Request27415.6 Bit Synchronous Circuit275Section 16 A/D Converter27716.1 Features27716.2 Input/Output Pins27916.3 Register Description28016.3.1 A/D Data Registers A to D (ADDRA to ADDRD)28016.3.2 A/D Control/Status Register (ADCSR)28116.3.3 A/D Control Register (ADCR)28216.4 Operation28316.4.1 Single Mode28316.4.2 Scan Mode28316.4.3 Input Sampling and A/D Conversion Time28416.4.4 External Trigger Input Timing28516.5 A/D Conversion Accuracy Definitions28616.6 Usage Notes28716.6.1 Permissible Signal Source Impedance28716.6.2 Influences on Absolute Precision287Section 17 Power-on Reset and Low-Voltage Detection Circuits (Optional)28917.1 Features28917.2 Register Descriptions29017.2.1 Low-Voltage-Detection Control Register (LVDCR)29017.2.2 Low-Voltage-Detection Status Register (LVDSR)29217.3 Operation29217.3.1 Power-on Reset Circuit29217.3.2 Low-Voltage Detection Circuit293Section 18 Power Supply Circuit29718.1 When Using the Internal Power Supply Step-Down Circuit29718.2 When Not Using the Internal Power Supply Step-Down Circuit298Section 19 Internal I/O Registers29919.1 Register Addresses29919.2 Register Bits30319.3 Registers States in Each Operating Mode306Section 20 Electrical Characteristics30920.1 Absolute Maximum Ratings30920.2 Electrical Characteristics (F-ZTAT™ Version)30920.2.1 Power Supply Voltage and Operating Ranges30920.2.2 DC Characteristics31120.2.3 AC Characteristics31720.2.4 A/D Converter Characteristics32120.2.5 Watchdog Timer Characteristics32220.2.6 Flash Memory Characteristics32320.2.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional)32520.3 Electrical Characteristics (Mask ROM Version)32620.3.1 Power Supply Voltage and Operating Ranges32620.3.2 DC Characteristics32720.3.3 AC Characteristics33320.3.4 A/D Converter Characteristics33720.3.5 Watchdog Timer33820.3.6 Power-Supply-Voltage Detection Circuit Characteristics (Optional)33920.4 Operation Timing33920.5 Output Load Circuit341Appendix A Instruction Set343A.1 Instruction List343A.2 Operation Code Map358A.3 Number of Execution States361A.4 Combinations of Instructions and Addressing Modes372Appendix B I/O Port Block Diagrams373B.1 I/O Port Block373B.2 Port States in Each Operating State389Appendix C Product Code Lineup390Appendix D Package Dimensions391Index393Tamaño: 2 MBPáginas: 397Language: EnglishManuales abiertas