Manual De UsuarioTabla de contenidosDescription3Features3Ordering Information3Key Parameters4Speed Grade4Address Table4Pin Descriptions5Input/Output Functional Descriptions6Pin Assignments8Registering Clock Driver Specifications10Capacitance Values10Input & Output Timing Requirements10On DIMM Thermal Sensor11Connection of Thermal Sensor11Temperature-to-Digital Conversion Performance11Functional Block Diagram124GB, 512Mx72 Module(1Rank of x8)128GB, 1Gx72 Module(1Rank of x4) - page1138GB, 1Gx72 Module(1Rank of x4) - page2148GB, 1Gx72 Module(2Rank of x8) - page1158GB, 1Gx72(2Rank of x8) - page21616GB, 2Gx72 Module(2Rank of x4) - page11716GB, 2Gx72 Module(2Rank of x4) - page21816GB, 2Gx72 Module(2Rank of x4) - page31932GB, 4Gx72 Module(4Rank of x4) - page12032GB, 4Gx72 Module(4Rank of x4) - page22132GB, 4Gx72 Module(4Rank of x4) - page32232GB, 4Gx72 Module(4Rank of x4) - page42332GB, 4Gx72 Module(4Rank of x4) - page524Absolute Maximum Ratings25Absolute Maximum DC Ratings25DRAM Component Operating Temperature Range25AC & DC Operating Conditions26Recommended DC Operating Conditions26AC & DC Input Measurement Levels28AC and DC Input Levels for Single-Ended Command and Address Signals28AC and DC Input Levels for Single-Ended Signals29Vref Tolerances30AC and DC Logic Input Levels for Differential Signals31Differential signal definition31Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)32note : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.32Single-ended requirements for differential signals33Differential Input Cross Point Voltage35Slew Rate Definitions for Single-Ended Input Signals36lew Rate Definitions for Differential Input Signals36AC & DC Output Measurement Levels37Single Ended AC and DC Output Levels37Differential AC and DC Output Levels37Single Ended Output Slew Rate38Differential Output Slew Rate39Reference Load for AC Timing and Output Slew Rate40Overshoot and Undershoot Specifications41Address and Control Overshoot and Undershoot Specifications41Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications42Refresh parameters by device density43Standard Speed Bins44DDR3L-800 Speed Bins44DDR3L-1066 Speed Bins45DDR3L-1333 Speed Bins46DDR3L-1600 Speed Bins47Speed Bin Table Notes48Environmental Parameters49IDD and IDDQ Specification Parameters and Test Conditions50IDD Specifications (Tcase: 0 to 95oC)624GB, 512M x 72 R-DIMM: HMT451R7MFR8A628GB, 1G x 72 R-DIMM: HMT41GR7MFR4A628GB, 1GM x 72 R-DIMM: HMT41GR7MFR8A6316GB, 2G x 72 R-DIMM: HMT42GR7MFR4A6332GB, 4G x 72 R-DIMM: HMT84GR7MMR4C64Module Dimensions65512Mx72 - HMT451R7MFR8A651Gx72 - HMT41GR7MFR4A661Gx72 - HMT41GR7MFR8A672Gx72 - HMT42GR7MFR4A682Gx72 - HMT42GR7MFR4A - Heat Spreader694Gx72 - HMT84GR7MMR4A704Gx72 - HMT84GR7MMR4A - Heat Spreader71Tamaño: 1 MBPáginas: 71Language: EnglishManuales abiertas
