Manual De Usuario (AT80580PJ0674ML)Tabla de contenidosIntel® Core™2 Extreme Processor QX9000D Series, Intel® Core™2 Quad Processor Q9000D, Q9000SD, Q8000D, and Q8000SD Series1Contents3Figures5Tables6Revision History7Intel® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, Q8000S Series Features91 Introduction111.1 Terminology121.1.1 Processor Terminology Definitions121.2 References142 Electrical Specifications152.1 Power and Ground Lands152.2 Decoupling Guidelines152.2.1 VCC Decoupling152.2.2 Vtt Decoupling152.2.3 FSB Decoupling162.3 Voltage Identification162.4 Reserved, Unused, and TESTHI Signals182.5 Power Segment Identifier (PSID)182.6 Voltage and Current Specification192.6.1 Absolute Maximum and Minimum Ratings192.6.2 DC Voltage and Current Specification202.6.3 VCC Overshoot252.6.4 Die Voltage Validation252.7 Signaling Specifications262.7.1 FSB Signal Groups262.7.2 CMOS and Open Drain Signals282.7.3 Processor DC Specifications282.7.3.1 Platform Environment Control Interface (PECI) DC Specifications292.7.3.2 GTL+ Front Side Bus Specifications302.8 Clock Specifications312.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking312.8.2 FSB Frequency Select Signals (BSEL[2:0])322.8.3 Phase Lock Loop (PLL) and Filter322.8.4 BCLK[1:0] Specifications323 Package Mechanical Specifications353.1 Package Mechanical Drawing353.2 Processor Component Keep-Out Zones393.3 Package Loading Specifications393.4 Package Handling Guidelines393.5 Package Insertion Specifications403.6 Processor Mass Specification403.7 Processor Materials403.8 Processor Markings404 Land Listing and Signal Descriptions434.1 Processor Land Assignments434.2 Alphabetical Signals Reference645 Thermal Specifications and Design Considerations755.1 Processor Thermal Specifications755.1.1 Thermal Specifications755.1.2 Thermal Metrology815.2 Processor Thermal Features815.2.1 Thermal Monitor815.2.2 Thermal Monitor 2825.2.3 On-Demand Mode835.2.4 PROCHOT# Signal845.2.5 THERMTRIP# Signal845.3 Platform Environment Control Interface (PECI)855.3.1 Introduction855.3.1.1 TCONTROL and TCC activation on PECI-Based Systems855.3.2 PECI Specifications865.3.2.1 PECI Device Address865.3.2.2 PECI Command Support865.3.2.3 PECI Fault Handling Requirements865.3.2.4 PECI GetTemp0() Error Code Support866 Features876.1 Power-On Configuration Options876.2 Clock Control and Low Power States876.2.1 Normal State886.2.2 HALT and Extended HALT Powerdown States886.2.2.1 HALT Powerdown State886.2.2.2 Extended HALT Powerdown State896.2.3 Stop Grant and Extended Stop Grant States896.2.3.1 Stop-Grant State896.2.3.2 Extended Stop Grant State906.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State906.2.4.1 HALT Snoop State, Stop Grant Snoop State906.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State906.2.5 Sleep State906.2.6 Deep Sleep State916.2.7 Deeper Sleep State916.2.8 Enhanced Intel SpeedStep® Technology926.3 Processor Power Status Indicator (PSI) Signal927 Boxed Processor Specifications937.1 Introduction937.2 Mechanical Specifications947.2.1 Boxed Processor Cooling Solution Dimensions947.2.2 Boxed Processor Fan Heatsink Weight957.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly957.3 Electrical Requirements957.3.1 Fan Heatsink Power Supply957.4 Thermal Specifications977.4.1 Boxed Processor Cooling Requirements977.4.2 Variable Speed Fan987.5 Boxed Intel® Core™2 Extreme Processor QX9650 Specifications997.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight1008 Debug Tools Specifications1038.1 Logic Analyzer Interface (LAI)1038.1.1 Mechanical Considerations1038.1.2 Electrical Considerations103Tamaño: 3 MBPáginas: 104Language: EnglishManuales abiertas
Manual De Usuario (AT80580AJ0674ML)Tabla de contenidosIntel® Core™2 Extreme Processor QX9000D Series, Intel® Core™2 Quad Processor Q9000D, Q9000SD, Q8000D, and Q8000SD Series1Contents3Figures5Tables6Revision History7Intel® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, Q8000S Series Features91 Introduction111.1 Terminology121.1.1 Processor Terminology Definitions121.2 References142 Electrical Specifications152.1 Power and Ground Lands152.2 Decoupling Guidelines152.2.1 VCC Decoupling152.2.2 Vtt Decoupling152.2.3 FSB Decoupling162.3 Voltage Identification162.4 Reserved, Unused, and TESTHI Signals182.5 Power Segment Identifier (PSID)182.6 Voltage and Current Specification192.6.1 Absolute Maximum and Minimum Ratings192.6.2 DC Voltage and Current Specification202.6.3 VCC Overshoot252.6.4 Die Voltage Validation252.7 Signaling Specifications262.7.1 FSB Signal Groups262.7.2 CMOS and Open Drain Signals282.7.3 Processor DC Specifications282.7.3.1 Platform Environment Control Interface (PECI) DC Specifications292.7.3.2 GTL+ Front Side Bus Specifications302.8 Clock Specifications312.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking312.8.2 FSB Frequency Select Signals (BSEL[2:0])322.8.3 Phase Lock Loop (PLL) and Filter322.8.4 BCLK[1:0] Specifications323 Package Mechanical Specifications353.1 Package Mechanical Drawing353.2 Processor Component Keep-Out Zones393.3 Package Loading Specifications393.4 Package Handling Guidelines393.5 Package Insertion Specifications403.6 Processor Mass Specification403.7 Processor Materials403.8 Processor Markings404 Land Listing and Signal Descriptions434.1 Processor Land Assignments434.2 Alphabetical Signals Reference645 Thermal Specifications and Design Considerations755.1 Processor Thermal Specifications755.1.1 Thermal Specifications755.1.2 Thermal Metrology815.2 Processor Thermal Features815.2.1 Thermal Monitor815.2.2 Thermal Monitor 2825.2.3 On-Demand Mode835.2.4 PROCHOT# Signal845.2.5 THERMTRIP# Signal845.3 Platform Environment Control Interface (PECI)855.3.1 Introduction855.3.1.1 TCONTROL and TCC activation on PECI-Based Systems855.3.2 PECI Specifications865.3.2.1 PECI Device Address865.3.2.2 PECI Command Support865.3.2.3 PECI Fault Handling Requirements865.3.2.4 PECI GetTemp0() Error Code Support866 Features876.1 Power-On Configuration Options876.2 Clock Control and Low Power States876.2.1 Normal State886.2.2 HALT and Extended HALT Powerdown States886.2.2.1 HALT Powerdown State886.2.2.2 Extended HALT Powerdown State896.2.3 Stop Grant and Extended Stop Grant States896.2.3.1 Stop-Grant State896.2.3.2 Extended Stop Grant State906.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State906.2.4.1 HALT Snoop State, Stop Grant Snoop State906.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State906.2.5 Sleep State906.2.6 Deep Sleep State916.2.7 Deeper Sleep State916.2.8 Enhanced Intel SpeedStep® Technology926.3 Processor Power Status Indicator (PSI) Signal927 Boxed Processor Specifications937.1 Introduction937.2 Mechanical Specifications947.2.1 Boxed Processor Cooling Solution Dimensions947.2.2 Boxed Processor Fan Heatsink Weight957.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly957.3 Electrical Requirements957.3.1 Fan Heatsink Power Supply957.4 Thermal Specifications977.4.1 Boxed Processor Cooling Requirements977.4.2 Variable Speed Fan987.5 Boxed Intel® Core™2 Extreme Processor QX9650 Specifications997.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight1008 Debug Tools Specifications1038.1 Logic Analyzer Interface (LAI)1038.1.1 Mechanical Considerations1038.1.2 Electrical Considerations103Tamaño: 3 MBPáginas: 104Language: EnglishManuales abiertas
Hoja De Datos (BX80580Q8400S)Tabla de contenidos1 Introduction91.1 Terminology101.1.1 Processor Terminology Definitions101.2 References122 Electrical Specifications132.1 Power and Ground Lands132.2 Decoupling Guidelines132.2.1 VCC Decoupling132.2.2 VTT Decoupling132.2.3 FSB Decoupling142.3 Voltage Identification142.4 Reserved, Unused, and TESTHI Signals162.5 Power Segment Identifier (PSID)162.6 Voltage and Current Specification172.6.1 Absolute Maximum and Minimum Ratings172.6.2 DC Voltage and Current Specification182.6.3 VCC Overshoot222.6.4 Die Voltage Validation232.7 Signaling Specifications232.7.1 FSB Signal Groups242.7.2 CMOS and Open Drain Signals252.7.3 Processor DC Specifications262.7.3.1 Platform Environment Control Interface (PECI) DC Specifications272.7.3.2 GTL+ Front Side Bus Specifications282.8 Clock Specifications292.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking292.8.2 FSB Frequency Select Signals (BSEL[2:0])302.8.3 Phase Lock Loop (PLL) and Filter312.8.4 BCLK[1:0] Specifications313 Package Mechanical Specifications353.1 Package Mechanical Drawing353.2 Processor Component Keep-Out Zones393.3 Package Loading Specifications393.4 Package Handling Guidelines393.5 Package Insertion Specifications403.6 Processor Mass Specification403.7 Processor Materials403.8 Processor Markings403.9 Processor Land Coordinates414 Land Listing and Signal Descriptions434.1 Processor Land Assignments434.2 Alphabetical Signals Reference665 Thermal Specifications and Design Considerations775.1 Processor Thermal Specifications775.1.1 Thermal Specifications775.1.2 Thermal Metrology815.2 Processor Thermal Features815.2.1 Thermal Monitor815.2.2 Thermal Monitor 2825.2.3 On-Demand Mode835.2.4 PROCHOT# Signal835.2.5 THERMTRIP# Signal845.3 Platform Environment Control Interface (PECI)855.3.1 Introduction855.3.1.1 TCONTROL and TCC activation on PECI-Based Systems855.3.2 PECI Specifications865.3.2.1 PECI Device Address865.3.2.2 PECI Command Support865.3.2.3 PECI Fault Handling Requirements865.3.2.4 PECI GetTemp0() Error Code Support866 Features876.1 Power-On Configuration Options876.2 Clock Control and Low Power States876.2.1 Normal State886.2.2 HALT and Extended HALT Powerdown States886.2.2.1 HALT Powerdown State886.2.2.2 Extended HALT Powerdown State896.2.3 Stop Grant and Extended Stop Grant States896.2.3.1 Stop-Grant State896.2.3.2 Extended Stop Grant State906.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State906.2.4.1 HALT Snoop State, Stop Grant Snoop State906.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State906.2.5 Sleep State906.2.6 Deep Sleep State916.2.7 Deeper Sleep State916.2.8 Enhanced Intel SpeedStep® Technology926.3 Processor Power Status Indicator (PSI) Signal927 Boxed Processor Specifications937.1 Introduction937.2 Mechanical Specifications947.2.1 Boxed Processor Cooling Solution Dimensions947.2.2 Boxed Processor Fan Heatsink Weight957.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly957.3 Electrical Requirements957.3.1 Fan Heatsink Power Supply957.4 Thermal Specifications977.4.1 Boxed Processor Cooling Requirements977.4.2 Variable Speed Fan998 Debug Tools Specifications1018.1 Logic Analyzer Interface (LAI)1018.1.1 Mechanical Considerations1018.1.2 Electrical Considerations101Tamaño: 1 MBPáginas: 102Language: EnglishManuales abiertas
