Manual De UsuarioTabla de contenidosAdvanced Features1Memory Management1Task Management1Protection Mechanisms1Support for Operating Systems1Memory Organization and Segmentation2Registers2General Registers2Index, Pointer, and Base Registers2Status and Control Registers2Addressing Modes2Memory Addressing Modes2Offset Computation2Memory Mode2Input/Output2Memory-Mapped I/O2Interrupts and Exceptions2Hierarchy of Instruction Sets2Data Movement Instructions3General-Purpose Data Movement Instructions3Stack Manipulation Instructions3Flag Operation with the Basic Instruction Set3Status Flags3Control Flags3Arithmetic Instructions3Addition Instructions3Subtraction Instructions3Multiplication Instructions3Division Instructions3Logical Instructions3Boolean Operation Instructions3Shift and Rotate Instructions3Shift Instructions3Rotate Instructions3Type Conversion and No-Operation Instructions3Test and Compare Instructions3Control Transfer Instructions3Unconditional Transfer Instructions3Jump Instruction3Call Instruction3Return and Return from Interrupt Instruction3Conditional Transfer Instructions3Loop Instructions3Software-Generated Interrupts3Software Interrupt Instruction3Character Translation and String Instructions3Translate Instruction3String Manipulation Instructions and Repeat Prefixes3Address Manipulation Instructions3Flag Control Instructions3Carry Flag Control Instructions3Direction Flag Control Instructions3Flag Transfer Instructions3Packed BCD Adjustment Instructions3Unpacked BCD Adjustment Instructions3Trusted and Privileged Restrictions on POPF and IRET3Machine State Instructions3Input and Output Instructions3Processor Extension Instructions3Processor Extension Synchronization Instructions3Numeric Data Processor Instructions3Arithmetic Instructions3Comparison Instructions3Transcendental Instructions3Data Transfer Instructions3Constant Instructions3Block I/O Instructions4High-Level Instructions4Addressing and Segmentation5Interrupt Handling5Interrupt Vector Table5Interrupt Priorities5Interrupt Procedures5Reserved and Dedicated Interrupt Vectors5System Initialization5Memory Management Overview6Descriptor Tables6Segments and Segment Descriptors6Segment Address Translation Registers6Introduction7Types of Protection7Protection Implementation7Memory Management and Protection7Separation of Address Spaces7LDT and GDT Access Checks7Type Validation7Privilege Levels and Protection7Example of Using Four Privilege Levels7Privilege Usage7Segment Descriptor7Data Accesses7Code Segment Access7Data Access Restriction by Privilege Level7POinter Privilege Stamping via ARPL7Gates7Call Gates7Intra-Level Transfers via Call Gate7Inter-Level Control Transfer via Call Gates7Inter-Level Returns7Introduction8Task State Segments and Descriptors8Task State Segment Descriptors8Task Switching8Task Linking8Task Gates8Interrupt Descriptor Table9Hardware Initiated Interrupts9Software Initiated Interrupts9Interrupt Gates and Trap Gates9Task Gates and Interrupt Tasks9Protection Exceptions and Reserved Vectors9Invalid OP-Code (Interrupt 6)9Double Fault (Interrupt 8)9Processor Extension Segment Overrun (Interrupt 9)9Invalid Task State Segment (Interrupt 10)9Not Present (Interrupt 11)9Stack Fault (Interrupt 12)9General Protection Fault (Interrupt 13)9Additional Exceptions and Interrupts9Single Step Interrupt (Interrupt 1)9Descriptor Table Registers10System Control Instructions10Machine Status Word10Privileged and Trusted Instructions10Initialization10Real Address Mode10Protected Mode10Conforming Code Segments11Pointer Validation11Pointer Integrity: RPL and the "Trojan Horse Problem"11NPX Context Switching11Bytes and Words in Memory280286 Base Architecture Register Set2Real Address Mode Segment Selector Interpretation2Protected Mode Segment Selector Interpretation280286 Stack2Stack Operation2BP Usage as a Stack Frame Base Pointer2Flags Register2Two-Component Address2Complex Addressing Modes2Memory-Mapped I/O2Hierarchy of Instructions2POP3POPA3SAL and SHL3SHR3SAR3ROL3ROR3RCL3RCR3LAHF and SAHF3PUSHF and POPF3Formal Definition of the ENTER Instruction4Variable Access in Nested Procedures4Stack Frame for MAIN at Level 14Stack Frame for Procedure C at Level 3 Called from B4Interrupt Vector Table for Real Address Mode5Format of the Segment Selector Component6Address Spaces and Task Isolation6Special Purpose Descriptors or System Segment Descriptors (S=O)6LDT Descriptor6Segment Descriptor Access Bytes6Memory Management Registers6Descriptor Loading6Addressing Segments of a Module within a Task7Local and Global Descriptor Table Definitions7Error Code Format (on the stack)7Selector Fields7Access Byte Examples7Pointer Privilege Stamping7Gate Descriptor Format7Call Gate7Stack Contents after an Inter-Level Call7Task State Segment and TSS Registers8Task Gate Descriptor8Task Switch Through a Task Gate8Interrupt Descriptor Table Definition9IDT Selector Error Code9Trap/Interrupt Gate Descriptors9Local and Global Descriptor Table Definition10Interrupt Descriptor Table Definition10Data Type for Global Descriptor Table and Interrupt Descriptor Table10Dynamic Segment Relocation and Expansion of Segment Limit11Example of NPX Context Switching11Implied Segment Usage by Index, Pointer, and Base Registers2Memory Operand Addressing Modes280286 Interrupt Vector Assignments (Real Address Mode)2Status Flags' Functions3Control Flags' Functions3Interpretation of Conditional Transfers3Interrupt Processing Order5Dedicated and Reserved Interrupt Vectors in Real Address Mode5Call Gate Checks7Inter-Level Return Checks7Checks Made during a Task Switch8Effect of a Task Switch on BUSY and NT Bits and the Link Word8Trap and Interrupt Gate Checks9Interrupt and Gate Interactions9Reserved Exceptions and Interrupts9Conditions That Invalidate the TSS9MSW 8it Functions10Recommended MSW Encodings for Processor Extension Control10NPXContextSwitching11ModRM Values8Hexadecimal Values for the Access Rights 8yte8+ 10000H1Introduction to the 80287 Numeric Processor Extension1Ease of Use1Applications1Upgradability1Hardware Interface180287 Numeric Processor Architecture1The NPX Status Word1Control Word1The NPXTag Word1The NPX Instruction and Data Pointers1Computation Fundamentals1Number System1Data Types and Formats1Binary Integers1Real Numbers1Rounding Control1Precision Control1Infinity Control1Special Computational Situations1Nonnormal Real Numbers1Denormals and Gradual Underflow1Un normals-Descendents of Denormal Operands1Infinity1NaN (Not a Number)1Indefinite1Numeric Exceptions1Invalid Operation1Zero Divisor1Denormalized Operand1Numeric Overflow and Underflow1Inexact Result1Software Exception Handling1Compatibility with the 8087 NPX2Numeric Operands2Arithmetic Instructions2Comparison Instructions2Constant Instructions2Instruction Set Reference Information2Instruction Execution Time2Instruction Length2Programming Facilities2High-Level Languages2ASM2862Defining Data2Addressing Modes2COlTlparative Programming Example2Instruction Synchronization2Data Synchronization2Error Synchronization2, Incorrect Error Synchronization2Real-Address Mode and Protected Virtual-Address Mode3Processor Initialization and Control3System Initialization3Recognizing the 80287 NPX3Initializing the 802873Handling Numeric Processing Exceptions3Exception Recovery· Examples3Conditional Bra,nching Examples4Exception Handling Examples4Floating-point to ASCII Conversion Examples4Function Partitioning4Special Instructions4Scalin"g the Value4Inaccur~cy in Scaling4Avoiding Underflow and Overflow4FPTAN and FPREM4Cosine Uses Sine Code4Evolution and Performance of Numeric Processors1'80287 NPX Block Diagram180287 Tag Word Format180287 Instruction and Data Pointer Image in Memory1FSAVE/FRSTOR Memory Layout2Sample 80287 Constants2Status Word RECORD Definition2Sample PL/M-286 Program2Sample ASM286 Program2Instructions and Register Stack2Nonconcurrent FIST Instruction Code Macro2Error Synchronization Examples2Software Routine to Recognize the 802873Conditional Branching for Compares4Conditional Branching for FXAM4Full-State Exception Handler4Reduced-Latency Exception Handler4Reentrant Exception Handler4Floating-Point to ASCII Conversion Routine4Calculating Trigonometric Functions4Numeric Processing Speed Comparisons1Numeric Data Types1Principal NPX Instructions1Interpreting the NPX Condition Codes1Real Number Notation1Rounding Modes1Denormalization Process1Unnormal Operands and Results1Zero Operands and Results1Masked Overflow Response with Directed Rounding1Infinity Operands and Results1Packed Decimal Encodings1Real and Long Real Encodings1Temporary Real Encodings1Exception Conditions and Masked Responses1Data Transfer Instructions2Arithmetic Instructions2Basic Arithmetic Instructions and Operands2Comparison Instructions2Condition Code Interpretation after FCOM2Condition Code Interpretation after FTST2Transcendental Instructions2Constant Instructions2Key to Operand Types2Execuiiur I PE:naitiE:52Instruction Set Reference Data2PLfM-286 Built-In Procedures2Addressing Mode Examples2NPX Processor State Following Initialization3Precedence of NPX Exceptions3Thh lub1'DUUnW will c.leul.t. the v.lue of 104PENNSYLVANIA i59714tt~/23040Tamaño: 30 MBPáginas: 515Language: EnglishManuales abiertas