Hoja De Datos (AV8062701084801)Tabla de contenidosContents3Figures6Tables7Revision History91.0 Introduction101.1 Supported Technologies111.2 Power Management Support121.3 Thermal Management Support121.4 Package Support131.5 Processor Testability131.6 Terminology131.7 Related Documents162.0 Interfaces182.1 System Memory Interface182.1.1 System Memory Technology Supported182.1.2 System Memory Timing Support192.1.3 Intel® Fast Memory Access (Intel® FMA)202.1.4 System Memory Frequency212.1.5 System Memory Organization Modes212.1.6 Data Scrambling222.2 Processor Graphics222.3 Processor Graphics Controller (GT)232.3.1 3D and Video Engines for Graphics Processing232.4 Digital Display Interface (DDI)252.5 Platform Environmental Control Interface (PECI)312.5.1 PECI Bus Architecture313.0 Technologies333.1 Intel® Virtualization Technology (Intel® VT)333.2 Intel® Trusted Execution Technology (Intel® TXT)373.3 Intel® Hyper-Threading Technology (Intel® HT Technology)383.4 Intel® Turbo Boost Technology 2.0393.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)393.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)393.7 Intel® 64 Architecture x2APIC403.8 Power Aware Interrupt Routing (PAIR)423.9 Execute Disable Bit423.10 Intel® Device Protection with Boot Guard423.11 Supervisor Mode Execution Protection (SMEP)423.12 Supervisor Mode Access Protection (SMAP)433.13 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)434.0 Power Management444.1 Advanced Configuration and Power Interface (ACPI) States Supported454.2 Processor Core Power Management464.2.1 Enhanced Intel® SpeedStep® Technology Key Features464.2.2 Low-Power Idle States474.2.3 Requesting Low-Power Idle States484.2.4 Core C-State Rules484.2.5 Package C-States504.2.6 Package C-States and Display Resolutions534.3 Integrated Memory Controller (IMC) Power Management544.3.1 Disabling Unused System Memory Outputs554.3.2 DRAM Power Management and Initialization554.3.2.1 Initialization Role of CKE564.3.2.2 Conditional Self-Refresh564.3.2.3 Dynamic Power-Down574.3.2.4 DRAM I/O Power Management574.3.3 DDR Electrical Power Gating (EPG)574.4 Graphics Power Management584.4.1 Intel® Rapid Memory Power Management (Intel® RMPM)584.4.2 Graphics Render C-State584.4.3 Intel® Smart 2D Display Technology (Intel® S2DDT)584.4.4 Intel® Graphics Dynamic Frequency584.4.5 Intel® Display Power Saving Technology (Intel® DPST)594.4.6 Intel® Automatic Display Brightness594.4.7 Intel® Seamless Display Refresh Rate Technology (Intel® SDRRS Technology)595.0 Thermal Management605.1 Thermal Considerations605.2 Intel® Turbo Boost Technology 2.0 Power Monitoring615.3 Intel® Turbo Boost Technology 2.0 Power Control615.3.1 Package Power Control615.3.2 Turbo Time Parameter625.4 Configurable TDP (cTDP) and Low-Power Mode625.4.1 Configurable TDP635.4.2 Low-Power Mode635.5 Thermal and Power Specifications645.6 Thermal Management Features665.6.1 Adaptive Thermal Monitor665.6.1.1 Thermal Control Circuit (TCC) Activation Offset675.6.1.2 Frequency / Voltage Control675.6.1.3 Clock Modulation675.6.2 Digital Thermal Sensor685.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy)695.6.2.2 Fan Speed Control with Digital Thermal Sensor695.6.3 PROCHOT# Signal695.6.3.1 Bi-Directional PROCHOT#695.6.3.2 Voltage Regulator Protection using PROCHOT#695.6.3.3 Thermal Solution Design and PROCHOT# Behavior705.6.3.4 Low-Power States and PROCHOT# Behavior705.6.3.5 THERMTRIP# Signal705.6.3.6 Critical Temperature Detection705.6.4 On-Demand Mode705.6.4.1 MSR Based On-Demand Mode715.6.4.2 I/O Emulation-Based On-Demand Mode715.6.5 Intel® Memory Thermal Management716.0 Signal Description726.1 System Memory Interface Signals726.2 Memory Compensation and Miscellaneous Signals746.3 Reset and Miscellaneous Signals746.4 embedded DisplayPort* (eDP*) Signals756.5 Display Interface Signals756.6 Testability Signals756.7 Error and Thermal Protection Signals766.8 Power Sequencing Signals776.9 Processor Power Signals776.10 Sense Signals786.11 Ground and Non-Critical to Function (NCTF) Signals786.12 Processor Internal Pull-Up / Pull-Down Terminations797.0 Electrical Specifications807.1 Integrated Voltage Regulator807.2 Power and Ground Pins807.3 VCC Voltage Identification (VID)807.4 Reserved or Unused Signals857.5 Signal Groups857.6 Test Access Port (TAP) Connection877.7 DC Specifications877.8 Voltage and Current Specifications877.8.1 Platform Environment Control Interface (PECI) DC Characteristics947.8.2 Input Device Hysteresis958.0 Package Specifications968.1 Package Mechanical Attributes968.2 Package Loading Specifications978.3 Package Storage Specifications979.0 Processor Ball and Signal Information989.1 Intel® Core™ M Processor Family Ball Information (BGA1234)989.2 U-Processor Ball Information (BGA1168)111Tamaño: 2 MBPáginas: 134Language: EnglishManuales abiertas