Hoja De Datos (FH8065501516710)Tabla de contenidosIntel® Atom™ Processor C2000 Product Family for Microserver1Volume 1: C2000 Product Family Program Overview301 Introduction and Product Offerings311.1 Overview311.2 Key Features321.3 Intel® Atom™ Processor C2000 Product Family for Microserver Block Diagram341.4 Product SKUs351.5 Datasheet Volume Structure and Scope361.6 Terminology381.7 Related Documents432 Multi-Core Intel® Atom™ Processors462.1 Signal Descriptions462.2 Features462.3 SoC Components472.3.1 SoC Core472.4 Features482.4.1 Intel® Virtualization Technology482.4.2 Intel® VT-x Objectives482.4.2.1 Intel® VT-x Features492.4.3 Security and Cryptography Technologies502.4.3.1 Advanced Encryption Standard New Instructions (AES-NI)502.4.3.2 PCLMULQDQ Instruction502.4.3.3 Digital Random Number Generator502.4.4 Intel® Turbo Boost Technology512.4.4.1 Intel® Turbo Boost Technology Frequency512.5 CPUID Instruction and SoC Identification52Volume 2: Functional563 Memory Controller573.1 Introduction573.2 Signal Descriptions573.3 Features583.3.1 Supported Memory Configuration583.3.2 System Memory Technology Supported583.3.3 System Memory Technology which is Not Supported593.4 RAS Features603.4.1 Data Parity Protection603.4.2 Memory Controller Error Correcting Codes (ECC)603.4.3 Demand and Patrol Scrubbing623.4.4 DDR3 Data Scrambling624 System Agent and Root Complex634.1 Introduction634.2 Signal Descriptions644.3 Features644.4 Root Complex654.4.1 Transaction Flow654.4.2 Root Complex Primary Transaction Routing664.5 Reliability, Availability and Serviceability (RAS)674.6 Error Classification684.6.1 Correctable Errors694.6.2 Fatal Errors694.6.3 Non-Fatal Errors694.6.3.1 Software Correctable Errors694.7 Global Error Reporting704.7.1 Reporting Errors to CPU724.7.1.1 Non-Maskable Interrupt (NMI)724.7.1.2 System Management Interrupt (SMI)724.7.2 Reporting Global Errors to an External Device724.7.3 Machine Check Architecture724.7.3.1 Machine Check Availability and Discovery754.7.3.2 P5 Compatibility MSRs754.7.3.3 Machine Check Global Control MSRs764.7.3.4 Machine Check Error-Reporting MSR Banks 0-5774.7.4 Error-Status Cloaking Feature884.7.4.1 Hide Corrected-Error Status From OS884.7.4.2 SMI for MCA Uncorrected Errors884.7.5 MCERR/IERR Signaling894.7.6 PCI Express INTx and MSI894.7.7 Error Register Overview904.7.7.1 Local Error Registers914.7.7.2 Global Error Registers934.7.7.3 System Error (SERR)954.7.7.4 First and Next Error Log Registers954.7.7.5 Error Register Flow964.7.7.6 Error Counters974.8 SoC Error Handling Summary984.9 Register Map1054.10 System Agent Register Map1064.10.1 Registers in Configuration Space1064.11 RAS Register Map1074.11.1 Registers in Configuration Space1074.12 Root Complex Event Collector (RCEC) Register Map1094.12.1 Registers in Configuration Space1095 Clock Architecture1115.1 Input Clocks1135.2 Output Clocks1146 Interrupt Architecture1156.1 PCI Interrupts and Routing1156.2 Non-Maskable Interrupt (NMI)1186.3 System Management Interrupt (SMI)1186.4 System Control Interrupt (SCI)1196.5 Message Signaled Interrupt (MSI and MSI-X)1196.6 I/O APIC Input Mapping1206.7 8259 PIC Input Mapping1226.8 Device Interrupt-Generating Capabilities1237 SoC Reset and Power Supply Sequences1257.1 Power Up from G3 State (Mechanical Off)1257.1.1 While in the G3 State1257.1.2 Powering-Up for the First Time1257.1.3 SUS Power Well Power-Up Sequence From the G3 State1267.1.4 Core Power-Up Sequence1297.2 Reset Sequences and Power-Down Sequences1337.2.1 Cold Reset Sequence1337.2.1.1 SUSPWRDNACK1387.2.2 Warm Reset Sequence1397.2.2.1 SPD Reset Sequence1407.2.3 Power-Down to S5 (Soft Off) and Stay There Sequence1417.2.4 Events While Sleeping in S5 (Soft-Off) State1417.2.4.1 S5 to S0 State1417.2.4.2 S5 to G3 State1427.2.4.3 SUS Well Power Down Sequence1427.2.5 Power-Down from S0 to G3 (Mechanical Off) Sequence1438 Thermal Management1448.1 Overview1448.2 Signal Descriptions1458.3 CPU Thermal Management Registers1468.4 Digital Thermal Sensors (DTS)1468.5 Thermal Interrupts and Thresholds1478.5.1 Core Programmable Thresholds1488.5.2 Core HOT Threshold1488.5.3 Core Out of Specification Threshold1488.5.4 Uncore Programmable Thresholds1498.5.4.1 Aux3 Trip1498.5.4.2 Aux2, Aux1, Aux0Trip1498.5.5 PROCHOT_B1498.5.6 MEMHOT_B1498.5.7 THERMTRIP_N Signal1498.6 Processor Thermal Control Circuit (TCC) Mechanisms1508.6.1 Clock Modulation (Intel® Thermal Monitor 1)1508.6.2 Core Frequency/Voltage Reduction (Intel® Thermal Monitor 2)1508.6.3 Thermal Status1508.7 Memory Thermal Control1518.7.1 Memory Bandwidth Counter1518.7.2 Memory Temperature Monitoring1519 Power Management1529.1 Overview1529.2 Signal Descriptions1539.3 Power Management Features1549.4 Internal Power Wells1559.4.1 Core Power Well1559.4.2 SUS Power Well1559.4.3 RTC Power Well1559.5 Supply Voltage Rails1569.6 Serial Voltage Identification (sVID) Controller1579.6.1 SVID VR Requirements1579.6.1.1 SVID Controller Addressing Requirements1579.6.2 Command Byte Encoding1579.6.2.1 sVID Commands1579.7 Active State Power Management Overview1599.8 System Global Power States1609.8.1 Low-Power S0 Idle1629.9 Processor Power States - C-States1639.10 Performance States1659.10.1 Processor Performance States - P-States1659.10.1.1 Frequency/Voltage Scaling1659.10.2 Software P-State Requests1669.10.2.1 Windows 7: P-State Transitions with ACNT/MCNT1669.11 Power Management Technologies1679.11.1 Intel® Turbo Boost Technology1679.11.1.1 Voltage Regulator Constraints1689.11.1.2 Thermal Design Power Constraints1689.11.2 Running Average Power Limiting (RAPL)1699.11.3 Always-On Timers (AONT)1699.11.4 I/O Device Controller Enable/Disable1699.12 Voltage Identification (VID) Table16910 System Address Maps17010.1 Physical Address Space Map17010.1.1 SoC Transaction Router Memory Map17110.1.1.1 Low MMIO17310.1.1.2 DOS DRAM17510.1.1.3 Additional Mappings17610.1.1.4 Isolated Memory Regions17610.1.2 I/O Fabric (MMIO) Map17710.2 I/O Address Space18010.2.1 SoC Transaction Router I/O Map18010.2.2 I/O Fabric I/O Map18010.2.2.1 PCU Fixed I/O Address Ranges18010.2.2.2 Variable I/O Address Ranges18210.3 PCI Configuration Space18410.4 Sideband Registers18710.4.1 Sideband Register Access18710.4.1.1 Sideband Registers for Address Mapping18811 Gigabit Ethernet (GbE) Controller18911.1 Introduction18911.2 Programmer’s Reference Manual19011.3 Feature List19011.4 Signal Descriptions19111.5 Architectural Overview19411.5.1 PCIe* Integrated Endpoint19511.5.2 Setting Up PCI Device Presence and Non-Presence19711.5.2.1 Soft Straps for GbE Controller19711.5.3 Disabling LAN Ports and PCI Functions by EEPROM19811.5.4 Disabling PCI Functions by BIOS19811.5.5 Mapping PCI Functions to LAN Ports19811.5.6 LAN Port Interface19911.5.7 Reference Clock Input20111.5.8 Pin Straps20111.5.9 LED Interface20211.5.10 Software-Defined Pins20311.5.11 SPI Interface20411.5.12 MDIO and I2C Interface20411.5.12.1 Sharing the MDIO0 Interface20511.5.13 SMBus and NC-SI Interface20711.5.13.1 SMBus 2.020711.5.13.2 NC-SI and REF_CLK20811.6 EEPROM20911.6.1 EEPROM Starter Images20911.6.2 EEPROM Map21111.6.3 Unique MAC Address21411.6.4 Read EEPROM Contents21411.6.5 Autoload from EEPROM and Resets21411.6.6 VLAN Support21411.7 Memory-Mapped I/O and Software Interface21511.8 System Manageability21511.9 Teaming Support21711.10 Register Map21812 PCI Express Root Ports (RP)21912.1 Signal Descriptions22012.2 Features22112.3 Architectural Overview22212.3.1 Peer-to-Peer Routing22212.3.2 Atomic Operations (AtomicOps) Routing22312.3.3 Reset Warn Technology22512.3.4 PCI Power Management Capability22512.3.4.1 Device Power Management States (D-States)22512.3.4.2 ASPM and ASPM Optionality22612.3.4.3 Power Management Event (PME) Signaling22612.3.4.4 Beacon and WAKE# Signaling22612.3.4.5 No Soft Reset Bit22612.3.5 PCI Bridge Subsystem Identification Capability22612.3.6 Message Signaled Interrupt (MSI) Capability22712.3.7 Advanced Error Reporting (AER) Capability22712.3.8 Access Control Services (ACS) Capability22712.4 PCI Configuration Process22812.4.1 I/O Address Transaction Forwarding22812.4.2 Non-Prefetchable Memory-Address Transaction Forwarding22912.4.3 Prefetchable Memory-Address Transaction Forwarding22912.4.4 Bus Master Enable (BME) in the Header Command Register23012.5 Interrupts and Events23112.5.1 Hot-Plug Events23212.5.2 System Error (SERR)23212.6 Power Management23212.7 Physical Layer23212.7.1 PCI Express Speed Support23212.7.2 Form Factor Support23212.8 Configuration of PCI Express Ports and Link Widths23312.8.1 Soft Straps and Bifurcation23412.8.2 PCI Express Lanes with Various SKUs Design Consideration23512.8.2.1 SoC PCI Express Lanes Mapping23612.9 PCI Express RAS Features23912.9.1 Error Detecting, Reporting and Logging23912.9.2 Data Poisoning24012.9.3 Link-Level Cyclical Redundancy Code (LCRC)24012.9.4 Link Retraining and Recovery24012.9.5 Unsupported Transactions and Unexpected Completions24012.9.6 Unconnected Ports24012.10 Register Maps24112.10.1 Registers in Configuration Space24212.10.2 PCI Capabilities24312.10.2.1 PCI Express Capability24312.10.2.2 PCI Power Management Capability24412.10.2.3 PCI Bridge Subsystem Vendor ID Capability24412.10.2.4 Message Signaled Interrupts (MSI) Capability24412.10.3 PCI Express Extended Capabilities24512.10.3.1 Advanced Error Reporting (AER) Extended Capability24512.10.3.2 Access Control Services (ACS) Extended Capability24512.10.3.3 Product-Specific Registers24513 SATA Controllers (SATA2, SATA3)24613.1 Signal Descriptions24713.2 Features24813.2.1 Supported Features24813.2.2 Theory of Operation24913.2.2.1 Standard ATA Emulation24913.2.2.2 48-Bit LBA Operation24913.2.3 SATA Swap Bay Support24913.2.4 Function Level Reset Support (FLR)25013.2.4.1 FLR Steps25013.2.5 Power Management Operation25113.2.5.1 Power State Mappings25113.2.5.2 Power State Transitions25113.2.5.3 SMI Trapping (APM)25213.2.6 SATA Device Presence25313.2.7 SATA LED25313.2.8 AHCI Operation25413.2.9 External SATA25413.3 Staggered Spin-Up Support25513.3.1 Staggered Spin-Up Operations in IDE Mode25513.3.2 Staggered Spin-Up Operation in AHCI Mode25513.4 Register Map25613.5 PCI Configuration Registers25713.6 Bus Master IDE I/O Registers25913.7 Serial ATA Index/Data Pair Superset Registers25913.8 Memory-Mapped Registers26014 Universal Serial Bus (USB) 2.026214.1 Signal Descriptions26314.2 Feature List26314.3 Architectural Overview26414.3.1 PCI Configuration Registers26614.3.2 Memory-Mapped I/O Registers26714.3.2.1 Host Controller Capability Registers26714.3.2.2 Host Controller Operational Registers26814.4 Enhanced Host Controller DMA26914.5 Data Encoding and Bit Stuffing27014.6 Packet Formats27014.7 EHC Initialization27014.7.1 Power-On27014.7.2 BIOS Initialization27014.7.3 Port Disable Override27114.7.4 Driver Initialization27114.7.5 EHC Resets27114.8 Sequence and Operating Modes27214.9 Interrupts and Error Conditions27314.9.1 Aborts on USB 2.0-Initiated Memory Reads27314.10 Power Management27414.10.1 Advanced Configuration and Power Interface (ACPI)27414.10.1.1 ACPI System States27514.10.2 Wake from System Suspend27514.10.3 Asynchronous Extended Sleep27514.10.4 EHCI Prefetch-Based Pause27514.10.5 EHCI Descriptor Cache27614.10.6 USB Internal Clock Shut Down27614.10.7 Memory Latency Tolerance27614.11 Security Features27714.11.1 Security Features27714.12 USB 2.0 Based Debug Port27714.12.1 Theory of Operation27814.12.1.1 OUT Transactions27914.12.1.2 IN Transactions28014.12.1.3 Debug Software28114.13 USB Over-Current Protection28314.14 Register Map28314.14.1 PCI Configuration and Capabilities28414.14.2 MMIO Registers28515 SMBus 2.0 Unit 1 - Host28615.1 Signal Descriptions28715.2 Features28715.3 Architectural Overview28815.4 Controller Characteristics and Operation29015.4.1 Electrical29015.4.2 SMBus Behavior on PCIe Reset29015.4.3 Addressing and Configuration29015.4.3.1 ARP Nomenclature29115.4.3.2 Unique Device Identifier (UDID) Format29215.4.3.3 ARP Slave Behavior29315.4.3.4 ARP Master Behavior29915.4.3.5 ARP Initialization Flow30215.4.4 SMT System Usage Models30415.4.5 SMT Security Requirements30415.4.6 SMT Timing Modes30415.4.7 SMT as Master30515.4.7.1 Hardware Buffering for Master Support30515.4.7.2 Master Descriptor30615.4.7.3 Master Descriptor Usage31015.4.7.4 Master Transactions Flow31415.4.7.5 Clearing of Start Bit31715.4.7.6 Master Retry Flow31815.4.7.7 Write Disabling to DIMM SPD EEPROM Addresses31915.4.8 SMT as Target31915.4.8.1 Hardware Buffering for Target Support31915.4.8.2 Target Descriptor32015.4.8.3 Target Transaction Status32315.4.8.4 Target Memory Buffer Hardware-Firmware Flow32715.4.8.5 Target Flow33015.4.9 Dynamic SMT Policy Update33915.4.9.1 Master Policy33915.4.9.2 Target Policy33915.5 Interrupts34115.5.1 Master Interrupts34215.5.2 Target Interrupts34315.5.3 Error Interrupts34415.5.4 Interrupt Cause Logging34515.6 SMT RAS Architecture34615.6.1 Soft Reset (DEVCTL.IFLR and GCTRL.SRST)34615.6.2 Target Reset (GCTRL.TRST)34715.7 MCTP Over SMBus Packet Header Format34815.8 Register Maps35015.8.1 Registers in Configuration Space35115.8.2 Registers in Memory Space35316 Platform Controller Unit (PCU)35516.1 Features35616.2 Pin-Based (Hard) Straps35716.3 Multi-Functional Signal Pins36016.3.1 Pins with More Than One Native Function36016.3.2 Pins of the Ethernet NC-SI Interface36116.4 Soft Straps36216.4.1 Flash Descriptor Soft Strap Definition36216.5 Root Complex Register Block (RCRB)37216.5.1 Boot BIOS Straps (BBS)37216.6 BIOS Ranges on Flash Memory Devices37316.6.1 BIOS Decode Enable for LPC and SPI37316.7 Register Map37416.7.1 PCI Configuration and Capabilities37516.7.2 MMIO Registers37516.7.3 Alternate Register Access Map37517 SMBus 2.0 Unit 2 - PECI37717.1 Signal Descriptions37817.2 PECI over SMBus Features37817.3 SMBus Supported Transactions37917.4 SMBus Block Read/Write Transaction Formats38017.5 SMBus Commands38117.6 PECI Over SMBus38217.6.1 PECI Message Header in SMBus38217.6.1.1 Target Address Field38317.6.1.2 Write Length Field38317.6.1.3 Read Length Field38317.6.1.4 Command Byte38317.6.2 PECI Write-Read Protocol38417.6.2.1 PECI Proxy Command Format38517.6.2.2 PECI Proxy Read Command38617.6.3 PECI Proxy Command Handling Procedure38817.6.4 PECI Proxy Command Trigger38917.6.4.1 Unsupported PECI Command38917.6.4.2 Illegally Formatted Command38917.7 PECI Proxy Commands39017.7.1 Ping()39117.7.2 GetDIB()39317.7.2.1 PECI Device Info Field39517.7.2.2 PECI Revision Number39517.7.3 GetTemp()39617.7.4 RdPkgConfig()39817.7.5 WrPkgConfig()40017.7.6 RdPCIConfigLocal()40317.7.7 RdEndPointConfig()40517.7.8 WrEndPointConfig()40717.8 DRAM Thermal Capabilities41017.8.1 DRAM Rank Temperature Write (Index = 18)41117.8.2 DRAM Channel Temperature Read (Index = 22)41117.9 CPU Thermal and Power Optimization Capabilities41217.9.1 Package Identifier Read (Index = 0)41617.9.1.1 CPU ID Information41617.9.1.2 Platform ID41617.9.1.3 Max Thread ID41617.9.1.4 CPU Microcode Update Revision41717.9.1.5 MCA Error Source Log41717.9.2 Package Power SKU Unit Read (Index = 30)41817.9.3 Package Power SKU Read (Index = 28 and 29)41917.9.4 Accumulated Run Time Read (Index = 31)42017.9.5 Package Temperature Read (Index = 2)42017.9.6 Per Core DTS Temperature Read (Index = 9)42017.9.7 Temperature Target Read (Index = 16)42117.9.8 Thermal Averaging Constant Write/Read (Index = 21)42117.9.9 Thermally Constrained Time Read (Index = 32)42217.9.10 Current Limit Read (Index = 17)42217.9.11 Accumulated Energy Status Read (Index = 3)42317.9.12 Package Power Limits For Multiple Turbo Modes (Index = 26 and 27)42417.9.13 Package Power Limit Performance Status Read (Index = 8)42617.9.14 Wake-on-PECI Mode Bit Write/Read (Index = 5)42617.9.15 SoC Power Budget (Index = 40)42617.10 DTS Temperature Data42717.10.1 PECI Device Temp Data42717.10.2 Interpretation42717.10.3 Temperature Filtering42717.10.4 Reserved Values42818 SMBus 2.0 Unit 0 - PCU42918.1 Signal Descriptions43018.2 General Architecture43018.3 System Host Controller43118.3.1 Command Protocols43118.3.1.1 Quick Command43118.3.1.2 Send Byte/Receive Byte Command43218.3.1.3 Write Byte/Word Command43218.3.1.4 Read Byte/Word Command43218.3.1.5 Process Call Command43318.3.1.6 Block Read/Write Command43418.3.1.7 Block Write-Block Read Process Call Command43518.3.1.8 I2C Read Command43618.3.2 Bus Arbitration43718.3.3 Bus Timing43718.3.3.1 Clock Stretching43718.3.3.2 Bus Time Out (the SoC as SMBus Master)43718.3.4 Interrupts and SMI43818.3.5 SMBALRT_N43818.3.6 SMBus CRC Generation and Checking43918.4 SMBus Slave Interface44018.4.1 Host Notify Command Format44018.5 Register Map44118.5.1 Registers in Configuration Space44218.5.2 Registers in Memory Space44318.5.3 Registers in I/O Space44419 Power Management Controller (PMC)44519.1 Signal Descriptions44619.2 Features44719.3 Architectural Overview44719.3.1 Reset Behavior44819.3.1.1 Overview44819.3.2 PMC Memory Area45019.3.2.1 PMC Function Disable Register45119.3.3 Exiting the G2 (S5) Soft-Off Power State45219.3.4 CPU INIT#, SMI and Reset Generation45319.3.5 ACPI Registers45419.3.6 Legacy Timers45519.3.6.1 TCO Watchdog Timer45519.3.7 Integrated PMC Microprocessor45519.4 Register Map45620 UART Controller45720.1 Signal Descriptions45820.2 Features45920.3 Architectural Overview45920.4 UART Operation46020.4.1 FIFO Operation46120.4.1.1 FIFO Interrupt Mode Operation46120.4.1.2 FIFO Polled Mode Operation46220.5 Registers46320.5.1 Register Map46320.5.2 PCI Configuration and Capabilities46420.5.3 Memory-Mapped I/O Registers46420.5.4 Fixed I/O Registers46421 Intel Legacy Block (iLB) Devices46521.1 Signal Descriptions46621.2 Features46721.2.1 Key Features46721.2.2 Non-Maskable Interrupt (NMI)46821.3 Register Map46921.3.1 Memory-Mapped I/O Registers46921.3.2 USB Port 64/60 Emulation47022 Serial Peripheral Interface (SPI)47122.1 Signal Descriptions47222.2 SPI Features47222.3 Architectural Overview47322.4 Operation Modes47422.4.1 Non-Descriptor Mode47422.4.2 Descriptor Mode47522.4.2.1 SPI Flash Regions47522.4.2.2 Flash Regions Sizes47522.5 Flash Descriptor47622.5.1 Master Section47822.5.2 Invalid Flash Descriptor Handling47822.5.3 Descriptor Security Override Strap47822.6 Flash Access47922.6.1 Direct Access47922.6.1.1 Security47922.6.2 Program Register Access48022.6.2.1 Security48022.7 Serial Flash Device Compatibility Requirements48122.7.1 BIOS SPI Flash Requirements48122.7.2 Hardware Sequencing Requirements48222.7.2.1 Single-Input, Dual-Output Fast Read48322.7.2.2 JEDEC ID48322.7.2.3 Error Correction and Detection48322.7.3 Multiple Page Write Usage Model48422.8 Soft Flash Protection48522.8.1 Flash Range Read and Write Protection48522.8.2 Global Write Protection48522.9 SPI Flash Device Recommended Pinout48522.10 Hardware vs. Software Sequencing48622.10.1 Hardware Sequencing48622.10.2 Software Sequencing48722.11 Register Map48822.11.1 Memory-Mapped Registers48922.11.1.1 BIOS Region (SPI_BIOS_PMA1)48923 Serial Interrupt Controller49123.1 Signal Descriptions49223.2 Architectural Overview49323.2.1 Controller and Protocol Overview49323.2.2 Start Frame49423.2.2.1 Continuous Mode and Quiet Mode49423.2.3 Data Frames49523.2.4 Stop Frame49523.2.5 Serial Interrupts Not Supported49523.2.6 Data Frame Format and Issues49623.3 Power Management49723.3.1 Clock Enabling49723.3.2 S0idle Support49723.4 Register Map49823.4.1 SERIRQ Registers in Memory Space49824 Low Pin Count (LPC) Controller49924.1 Signal Descriptions50024.2 Architectural Overview50224.2.1 No DMA or PHOLD Support50224.2.2 LPC Flash Programming Considerations50324.2.2.1 Overview50324.2.2.2 Boot BIOS Strap50424.2.2.3 LPC Cycle Decoding50424.2.2.4 LPC Notes50424.2.3 Intel® Trusted Platform Module (Intel® TPM)50524.2.4 LPC as the System Subtractive Agent50524.2.5 Port 80 POST Code Register Redirection50624.2.6 System Error (SERR)50624.3 Power Management50624.3.1 LPCPD# Protocol50624.3.2 Clock Run (CLKRUN)50624.3.3 LPC Clock Enabling50624.4 BIOS and Firmware Flash Memory50724.5 Register Map50824.5.1 PCI Configuration and Capabilities50924.5.2 Memory-Mapped I/O Register51025 General-Purpose I/O (GPIO)51125.1 Signal Descriptions51225.2 Features51325.3 Architectural Overview51325.3.1 Choosing the Native Signal Mode or Customer GPIO Mode51425.3.1.1 SC_USE_SEL and SUS_USE_SEL Registers51525.3.2 Electrical Configuration Registers for GPIO Ports51525.3.3 Using Customer GPIOs in a Board Design51525.3.4 GPI-Signaled Events51825.3.5 Wake-up Events51825.4 Register Map51926 Real Time Clock (RTC)52026.1 Signal Descriptions52126.2 Features52226.3 Architectural Overview52326.3.1 Update Cycles52326.3.2 Interrupts52326.3.3 Lockable RAM Ranges52326.4 RTC During Power-Up52426.5 Clearing the Battery-Backed RTC RAM52426.5.1 Using SRTCRST_B to Clear CMOS Registers52426.5.2 Using a GPI to Clear CMOS Registers52526.6 Support of S0idle Power-Saving Mechanism52626.7 Register Map52626.7.1 Registers in I/O Space52726.7.2 Difficulty Accessing These Registers52727 8254 Programmable Interval Timer (PIT)52827.1 Signal Descriptions52927.2 Features52927.3 Architectural Overview53027.3.1 Timer Control Word (TCW)53027.3.1.1 Read Back Command53027.3.1.2 Counter Latch Command53127.3.2 Counter 0, System Timer53227.3.3 Counter 1, Refresh Request Signal53227.3.4 Counter 2, Speaker Tone53227.3.5 NMI Status and Control (NSC)53227.4 Programming the 8254 Counters53327.5 Reading from the Interval Timer53427.5.1 Simple Read53427.5.2 Counter Latch Command53427.5.3 Read-Back Command53527.6 Register Map53627.6.1 I/O Mapped Registers53728 High Precision Event Timer (HPET)53928.1 Signal Descriptions54028.2 Features54028.3 Architectural Overview54128.3.1 Configuration Registers54128.3.2 Timer Comparator54128.3.3 Interrupts54128.3.4 Timer Accuracy54228.4 Programming the HPET54328.4.1 Non-Periodic Mode - All Timers54328.4.2 Periodic Mode - Timer 0 Only54328.4.3 Programming Timer Interrupts54428.4.3.1 Mapping Option #1: Legacy Option (GCFG.LRE Set)54428.4.3.2 Mapping Option #2: Standard Option (GCFG.LRE Cleared)54428.4.4 Support of S0idle Power-Saving Mechanism54428.5 Register Map54528.5.1 Memory-Mapped Registers54629 8259 Programmable Interrupt Controller (PIC)54729.1 Signal Descriptions54729.2 Architectural Overview54829.2.1 Interrupt Handling55029.2.1.1 Generating Interrupts55029.2.1.2 Acknowledging Interrupts55029.2.1.3 Hardware/Software Interrupt Sequence55129.2.2 Initialization Command Words (ICWx)55229.2.2.1 ICW155229.2.2.2 ICW255229.2.2.3 ICW355229.2.2.4 ICW455229.2.3 Operation Command Words (OCW)55329.3 Operation55429.3.1 Fully-Nested Mode55429.3.2 Special Fully-Nested Mode55429.3.3 Automatic Rotation Mode (Equal Priority Devices)55429.3.4 Specific Rotation Mode (Specific Priority)55429.3.5 Poll Mode55529.3.6 Edge- and Level-Triggered Mode55529.3.7 End of Interrupt (EOI) Operations55529.3.8 Normal End of Interrupt55629.3.9 Automatic End of Interrupt Mode55629.3.10 Masking Interrupts55729.3.10.1 Masking on an Individual Interrupt Request55729.3.10.2 Special Mask Mode55729.4 Register Map55829.4.1 I/O Mapped Registers55930 I/O Advanced APIC (I/O APIC)56130.1 Signal Descriptions56230.2 Features56230.3 Architectural Overview56230.3.1 APIC ID and Version Registers56330.3.2 Interrupt Redirection Registers56330.3.3 Accessing the I/O APIC Internal Registers56330.3.3.1 Identification (ID) Register56430.3.3.2 Version (VS) Register56430.3.3.3 Redirection Table Entry (RTE[23:0]) Registers56530.3.4 End Of Interrupt (EOI) Register56630.4 Register Map56730.4.1 Memory-Mapped Registers568Volume 3: Electrical, Mechanical, and Thermal56931 Signal Names and Descriptions57031.1 Overview57031.2 Name Convention57231.3 System DDR Memory Signals57431.4 Thermal Signals58431.5 SVID Signals58531.6 Miscellaneous Signals58631.7 SATA2 Signals58831.8 SATA3 Signals59031.9 PCIe Signals59231.10 GbE, SMBus, and NC-SI Signals59331.11 LPC Interface Signals59931.12 RTC Well Signals60131.13 GPIO SUS Signals60331.14 PMU Signals60431.15 USB 2 Signals60631.16 SPI Signals60731.17 GPIO DFX Signals60831.18 Clock Receiver Signals60931.19 Tap Port/ITP Signals61031.20 Reserved Signals61131.21 Signal Pins with Shared Functions or GPIO61232 Signal Pin States and Termination61832.1 Signal Pin States61832.1.1 System Memory Signals61932.1.1.1 DDR3[0] Memory Signals61932.1.1.2 DDR3[1] Memory Signals62032.1.2 Thermal Management Signals62132.1.3 SVID Interface Signals62132.1.4 Core Misc Signals62132.1.5 SATA/eSATA GEN2 Interface Signals62232.1.6 SATA3 Interface Signals62232.1.7 PCI Express Root Port Signals62332.1.8 GbE Interface Signals62432.1.9 EEPROM Signals62532.1.10 Low Pin Count (LPC) Signals62532.1.11 Intel Legacy Block (ILB) Signals62532.1.12 RTC Well Signals62532.1.13 GPIO SUS Signals62632.1.14 Power Management Unit (PMU) Interface62632.1.15 USB2 Interface Signals62632.1.16 SPI and Flash Memory Signals62732.1.17 GPIO DFX Signals62732.1.18 CLK Interface62732.1.19 JTAG and Debug Signals62832.1.20 General-Purpose I/O Signals62832.2 Integrated Termination Resistors62932.3 Strap Signals63032.4 Reserved Signals and Signals Not Used by Platform Board63033 Signal Electrical and Timing Characteristics63133.1 DDR3 Memory Interface63133.1.1 DC Specifications63133.1.2 AC Specifications63333.1.2.1 DDR3 1333 MT/s63333.1.2.2 DDR3 1600 MT/s63533.1.3 Interface Timing Parameters and Waveforms63733.1.4 DDR3 Signal Quality Specifications63933.1.4.1 Overshoot/Undershoot Magnitude63933.1.4.2 Overshoot/Undershoot Pulse Duration64033.1.5 Other DDR3 Controller Electrical Specifications64133.2 PCI Express Root Port Interface64233.3 2.5 and 1 Gigabit Ethernet (GbE) Interface64333.3.1 SGMII (MAC to PHY)64333.3.2 1000BASE-KX (1 GbE)64333.3.3 2500BASE-X (2.5 GbE)64433.3.3.1 Transmitter Characteristics64433.3.3.2 Receiver Characteristics65133.4 Network Controller MDIO Interface65333.5 Network Controller Sideband Interface (NC-SI)65433.6 Network Controller EEPROM Interface65533.6.1 DC Specifications65533.6.2 Interface Timing Parameters and Waveforms65633.7 Network Controller Miscellaneous Interfaces65733.7.1 GbE SMBus 2.0 Interface65733.7.2 GbE LED and Software-Defined Pins (SDP)65733.8 SATA2 and SATA3 Controller Interfaces65833.9 USB 2.0 Interface65933.10 SMBus 2.0 Interfaces66033.10.1 DC Specifications66033.10.2 Interface Timing Parameters and Waveforms66133.11 Low Pin Count (LPC) Interface66333.12 Serial Peripheral Interface (SPI) Bus Interface66433.12.1 DC Specifications66433.12.2 Interface Timing Parameters and Waveforms66433.13 High-Speed UART Interface66633.13.1 DC Specifications66633.13.2 Interface Timing Parameters and Waveforms66633.14 Speaker Interface66833.14.1 DC Specifications66833.15 Customer General-Purpose I/O (GPIO) Interfaces66833.15.1 DC Specifications66833.16 SoC Reference Clock Interfaces66933.16.1 Host, DDR3, PCI Express, SATA2 Reference Clocks66933.16.2 GbE Reference Clock67133.16.3 SATA3 Reference Clock67233.16.3.1 With Spread Spectrum67233.16.3.2 With no Spread Spectrum67233.16.4 USB 2.0 Reference Clock67333.16.5 14.318 MHz Reference Clock67433.17 General Clocks Provided by SoC Interfaces67533.17.1 DC Specifications67533.17.2 Interface Timing Parameters and Waveforms67633.18 SoC Error-Signal Interface67733.18.1 DC Specifications67733.19 SoC Reset and Power Management Unit (PMU) Interface67833.19.1 DC Specifications67833.19.2 Interface Timing Parameters and Waveforms67833.20 SoC Real-Time Clock (RTC) Interface67933.20.1 DC Specifications67933.20.2 RTC Crystal Specifications68033.20.3 Interface Timing Parameters and Waveforms68033.21 SoC Thermal Management Interface68133.21.1 DC Specifications68133.22 SoC Serial VID (SVID) Interface68233.22.1 DC Specifications68233.22.2 Interface Timing Parameters and Waveforms68333.23 SoC JTAG and Debug Interfaces68433.23.1 DC Specifications68433.23.2 Interface Timing Parameters and Waveforms68633.24 Waveform Figures Commonly Referenced68834 Operating Conditions and Power Requirements68934.1 Absolute Maximum and Minimum Ratings68934.1.1 Component Storage Conditions Specification68934.1.1.1 Prior to Board-Attach68934.1.1.2 Post Board-Attach69034.2 Normal Operating Conditions69034.2.1 Temperature69034.2.2 Supply Voltage and Current Requirements69134.2.3 Voltage Supply Pins and VR Groups69635 Component Ball-Out Listing69935.1 Ball Map72236 Mechanical Characteristics745Tamaño: 9 MBPáginas: 746Language: EnglishManuales abiertas
