Hoja De Datos (BX80623G640T)Tabla de contenidosContents3Figures5Tables6Intel® Pentium® Dual-Core Desktop Processor E2000D Series7Revision History8Intel® Pentium® Dual-Core Desktop Processor E2000D Series11 Introduction91.1 Terminology91.1.1 Processor Terminology101.2 References112 Electrical Specifications132.1 Power and Ground Lands132.2 Decoupling Guidelines132.2.1 VCC Decoupling132.2.2 VTT Decoupling132.2.3 FSB Decoupling142.3 Voltage Identification142.4 Market Segment Identification (MSID)162.5 Reserved, Unused, and TESTHI Signals162.6 Voltage and Current Specification172.6.1 Absolute Maximum and Minimum Ratings172.6.2 DC Voltage and Current Specification192.6.3 Vcc Overshoot212.6.4 Die Voltage Validation222.7 Signaling Specifications222.7.1 FSB Signal Groups232.7.2 CMOS and Open Drain Signals242.7.3 Processor DC Specifications252.7.3.1 GTL+ Front Side Bus Specifications262.8 Clock Specifications282.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking282.8.2 FSB Frequency Select Signals (BSEL[2:0])282.8.3 Phase Lock Loop (PLL) and Filter292.8.4 BCLK[1:0] Specifications (CK505 based Platforms)292.8.5 BCLK[1:0] Specifications (CK410 based Platforms)312.9 PECI DC Specifications323 Package Mechanical Specifications333.1 Package Mechanical Drawing333.2 Processor Component Keep-Out Zones373.3 Package Loading Specifications373.4 Package Handling Guidelines373.5 Package Insertion Specifications383.6 Processor Mass Specification383.7 Processor Materials383.8 Processor Markings383.9 Processor Land Coordinates394 Land Listing and Signal Descriptions414.1 Processor Land Assignments414.2 Alphabetical Signals Reference645 Thermal Specifications and Design Considerations735.1 Processor Thermal Specifications735.1.1 Thermal Specifications735.1.2 Thermal Metrology775.2 Processor Thermal Features775.2.1 Thermal Monitor775.2.2 Thermal Monitor 2785.2.3 On-Demand Mode795.2.4 PROCHOT# Signal805.2.5 THERMTRIP# Signal805.3 Thermal Diode815.4 Platform Environment Control Interface (PECI)835.4.1 Introduction835.4.1.1 Key Difference with Legacy Diode-Based Thermal Management835.4.2 PECI Specifications855.4.2.1 PECI Device Address855.4.2.2 PECI Command Support855.4.2.3 PECI Fault Handling Requirements855.4.2.4 PECI GetTemp0() Error Code Support856 Features876.1 Power-On Configuration Options876.2 Clock Control and Low Power States886.2.1 Normal State886.2.2 HALT and Extended HALT Powerdown States886.2.2.1 HALT Powerdown State896.2.2.2 Extended HALT Powerdown State896.2.3 Stop Grant and Extended Stop Grant States896.2.3.1 Stop-Grant State906.2.3.2 Extended Stop Grant State906.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State906.2.4.1 HALT Snoop State, Stop Grant Snoop State906.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State916.3 Enhanced Intel SpeedStep® Technology917 Boxed Processor Specifications937.1 Mechanical Specifications947.1.1 Boxed Processor Cooling Solution Dimensions947.1.2 Boxed Processor Fan Heatsink Weight967.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly967.2 Electrical Requirements967.2.1 Fan Heatsink Power Supply967.3 Thermal Specifications987.3.1 Boxed Processor Cooling Requirements987.3.2 Fan Speed Control Operation (Intel® Pentium® Dual-Core Desktop Processor E2000 Series)1008 Debug Tools Specifications1038.1 Logic Analyzer Interface (LAI)1038.1.1 Mechanical Considerations1038.1.2 Electrical Considerations103Tamaño: 1 MBPáginas: 104Language: EnglishManuales abiertas
Manual De Usuario (CM8062301002204)Tabla de contenidos1 Introduction112 Processor Configuration Registers132.1 Register Terminology132.2 PCI Devices and Functions on Processor142.3 System Address Map152.3.1 Legacy Address Range182.3.2 Main Memory Address Range (1 MB – TOLUD)202.3.3 PCI Memory Address Range (TOLUD – 4 GB)232.3.4 Main Memory Address Space (4 GB to TOUUD)262.3.5 PCI Express* Configuration Address Space322.3.6 PCI Express* Graphics Attach (PEG)332.3.7 Graphics Memory Address Ranges342.3.8 System Management Mode (SMM)352.3.9 SMM and VGA Access through GTT TLB352.3.10 Intel® Management Engine (Intel ME) Stolen Memory Accesses352.3.11 I/O Address Space362.3.12 Management Component Transport Protocol (MCTP) and Kernel-based Virtual Machine (KVM) Flows372.3.13 Decode Rules and Cross-Bridge Address Mapping372.4 Processor Register Introduction452.4.1 I/O Mapped Registers462.5 PCI Device 0, Function 0 Configuration Registers462.5.1 VID—Vendor Identification Register482.5.2 DID—Device Identification Register482.5.3 PCICMD—PCI Command Register492.5.4 PCISTS—PCI Status Register502.5.5 RID—Revision Identification Register522.5.6 CC—Class Code Register532.5.7 HDR—Header Type Register532.5.8 SVID—Subsystem Vendor Identification Register542.5.9 SID—Subsystem Identification Register542.5.10 PXPEPBAR—PCI Express Egress Port Base Address Register552.5.11 MCHBAR—Host Memory Mapped Register Range Base Register562.5.12 GGC—GMCH Graphics Control Register Register572.5.13 DEVEN—Device Enable Register592.5.14 PCIEXBAR—PCI Express Register Range Base Address Register602.5.15 DMIBAR—Root Complex Register Range Base Address Register622.5.16 PAM0—Programmable Attribute Map 0 Register632.5.17 PAM1—Programmable Attribute Map 1 Register642.5.18 PAM2—Programmable Attribute Map 2 Register652.5.19 PAM3—Programmable Attribute Map 3 Register662.5.20 PAM4—Programmable Attribute Map 4 Register672.5.21 PAM5—Programmable Attribute Map 5 Register682.5.22 PAM6—Programmable Attribute Map 6 Register692.5.23 LAC—Legacy Access Control Register702.5.24 REMAPBASE—Remap Base Address Register742.5.25 REMAPLIMIT—Remap Limit Address Register742.5.26 TOM—Top of Memory Register752.5.27 TOUUD—Top of Upper Usable DRAM Register762.5.28 BDSM—Base Data of Stolen Memory Register772.5.29 BGSM—Base of GTT stolen Memory Register772.5.30 G Memory Base Register782.5.31 TOLUD—Top of Low Usable DRAM Register792.5.32 SKPD—Scratchpad Data Register802.5.33 CAPID0_A—Capabilities A Register812.6 PCI Device 1, Function 0–2 Configuration Registers832.6.1 VID1—Vendor Identification Register852.6.2 DID1—Device Identification Register852.6.3 PCICMD1—PCI Command Register862.6.4 PCISTS1—PCI Status Register882.6.5 RID1—Revision Identification Register902.6.6 CC1—Class Code Register902.6.7 CL1—Cache Line Size Register912.6.8 HDR1—Header Type Register912.6.9 PBUSN1—Primary Bus Number Register912.6.10 SBUSN1—Secondary Bus Number Register922.6.11 SUBUSN1—Subordinate Bus Number Register922.6.12 IOBASE1—I/O Base Address Register932.6.13 IOLIMIT1—I/O Limit Address Register932.6.14 SSTS1—Secondary Status Register942.6.15 MBASE1—Memory Base Address Register952.6.16 MLIMIT1—Memory Limit Address Register962.6.17 PMBASE1—Prefetchable Memory Base Address Register972.6.18 PMLIMIT1—Prefetchable Memory Limit Address Register982.6.19 PMBASEU1—Prefetchable Memory Base Address Upper Register992.6.20 PMLIMITU1—Prefetchable Memory Limit Address Upper Register1002.6.21 CAPPTR1—Capabilities Pointer Register1002.6.22 INTRLINE1—Interrupt Line Register1012.6.23 INTRPIN1—Interrupt Pin Register1012.6.24 BCTRL1—Bridge Control Register1022.6.25 PM_CAPID1—Power Management Capabilities Register1042.6.26 PM_CS1—Power Management Control/Status Register1052.6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register1062.6.28 SS—Subsystem ID and Subsystem Vendor ID Register1072.6.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register1072.6.30 MC—Message Control Register1082.6.31 MA—Message Address Register1092.6.32 MD—Message Data Register1092.6.33 PEG_CAPL—PCI Express-G Capability List Register1092.6.34 PEG_CAP—PCI Express-G Capabilities Register1102.6.35 DCAP—Device Capabilities Register1102.6.36 DCTL—Device Control Register1112.6.37 DSTS—Device Status Register1122.6.38 LCTL—Link Control Register1132.6.39 LSTS—Link Status Register1152.6.40 SLOTCAP—Slot Capabilities Register1162.6.41 SLOTCTL—Slot Control Register1182.6.42 SLOTSTS—Slot Status Register1202.6.43 RCTL—Root Control Register1222.6.44 LCTL2—Link Control 2 Register1232.7 PCI Device 1, Function 0–2 Extended Configuration Registers1252.7.1 PVCCAP1—Port VC Capability Register 11252.7.2 PVCCAP2—Port VC Capability Register 21262.7.3 PVCCTL—Port VC Control Register1262.7.4 VC0RCAP—VC0 Resource Capability Register1272.7.5 VC0RCTL—VC0 Resource Control Register1282.7.6 VC0RSTS—VC0 Resource Status Register1292.7.7 PEG_TC—PCI Express Completion Time-out Register1292.8 PCI Device 2 Configuration Registers1302.8.1 VID2—Vendor Identification Register1312.8.2 DID2—Device Identification Register1312.8.3 PCICMD2—PCI Command Register1322.8.4 PCISTS2—PCI Status Register1332.8.5 RID2—Revision Identification Register1342.8.6 CC—Class Code Register1342.8.7 CLS—Cache Line Size Register1352.8.8 MTXT2—Master Latency Timer Register1352.8.9 HDR2—Header Type Register1352.8.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address Register1362.8.11 GMADR—Graphics Memory Range Address Register1372.8.12 IOBAR—I/O Base Address Register1382.8.13 SVID2—Subsystem Vendor Identification Register1382.8.14 SID2—Subsystem Identification Register1392.8.15 ROMADR—Video BIOS ROM Base Address Register1392.8.16 INTRPIN—Interrupt Pin Register1392.8.17 MINGNT—Minimum Grant Register1402.8.18 MAXLAT—Maximum Latency Register1402.8.19 MSAC—Multi Size Aperture Control Register1412.9 Device 2 I/O Registers1422.9.1 INDEX—MMIO Address Register1422.9.2 DATA—MMIO Data Register1422.10 PCI Device 6 Configuration Registers1432.10.1 VID6—Vendor Identification Register1442.10.2 DID6—Device Identification Register1452.10.3 PCICMD6—PCI Command Register1452.10.4 PCISTS6—PCI Status Register1472.10.5 RID6—Revision Identification Register1492.10.6 CC6—Class Code Register1492.10.7 CL6—Cache Line Size Register1502.10.8 HDR6—Header Type Register1502.10.9 PBUSN6—Primary Bus Number Register1502.10.10 SBUSN6—Secondary Bus Number Register1512.10.11 SUBUSN6—Subordinate Bus Number Register1512.10.12 IOBASE6—I/O Base Address Register1522.10.13 IOLIMIT6—I/O Limit Address Register1522.10.14 SSTS6—Secondary Status Register1532.10.15 MBASE6—Memory Base Address Register1542.10.16 MLIMIT6—Memory Limit Address Register1552.10.17 PMBASE6—Prefetchable Memory Base Address Register1562.10.18 PMLIMIT6—Prefetchable Memory Limit Address Register1572.10.19 PMBASEU6—Prefetchable Memory Base Address Upper Register1582.10.20 PMLIMITU6—Prefetchable Memory Limit Address Upper Register1592.10.21 CAPPTR6—Capabilities Pointer Register1592.10.22 INTRLINE6—Interrupt Line Register1602.10.23 INTRPIN6—Interrupt Pin Register1602.10.24 BCTRL6—Bridge Control Register1612.10.25 PM_CAPID6—Power Management Capabilities Register1632.10.26 PM_CS6—Power Management Control/Status Register1642.10.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register1652.10.28 SS—Subsystem ID and Subsystem Vendor ID Register1662.10.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register1662.10.30 MC—Message Control Register1672.10.31 MA—Message Address Register1682.10.32 MD—Message Data Register1682.10.33 PEG_CAPL—PCI Express-G Capability List Register1682.10.34 PEG_CAP—PCI Express-G Capabilities Register1692.10.35 DCAP—Device Capabilities Register1692.10.36 DCTL—Device Control Register1702.10.37 DSTS—Device Status Register1712.10.38 LCTL—Link Control Register1722.10.39 LSTS—Link Status Register1742.10.40 SLOTCAP—Slot Capabilities Register1752.10.41 SLOTCTL—Slot Control Register1772.10.42 SLOTSTS—Slot Status Register1792.10.43 RCTL—Root Control Register1802.11 PCI Device 6 Extended Configuration Registers1812.11.1 PVCCAP1—Port VC Capability Register 11812.11.2 PVCCAP2—Port VC Capability Register 21822.11.3 PVCCTL—Port VC Control Register1822.11.4 VC0RCAP—VC0 Resource Capability Register1832.11.5 VC0RCTL—VC0 Resource Control Register1842.11.6 VC0RSTS—VC0 Resource Status Register1852.12 DMIBAR Registers1862.12.1 DMIVCECH—DMI Virtual Channel Enhanced Capability Register1872.12.2 DMIPVCCAP1—DMI Port VC Capability Register 11882.12.3 DMIPVCCAP2—DMI Port VC Capability Register 21882.12.4 DMIPVCCTL—DMI Port VC Control Register1892.12.5 DMIVC0RCAP—DMI VC0 Resource Capability Register1892.12.6 DMIVC0RCTL—DMI VC0 Resource Control Register1902.12.7 DMIVC0RSTS—DMI VC0 Resource Status Register1912.12.8 DMIVC1RCAP—DMI VC1 Resource Capability Register1912.12.9 DMIVC1RCTL—DMI VC1 Resource Control Register1922.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register1932.12.11 DMIVCPRCAP—DMI VCp Resource Capability Register1932.12.12 DMIVCPRCTL—DMI VCp Resource Control Register1942.12.13 DMIVCPRSTS—DMI VCp Resource Status Register1952.12.14 DMIESD—DMI Element Self Description Register1962.12.15 DMILE1D—DMI Link Entry 1 Description Register1972.12.16 DMILE1A—DMI Link Entry 1 Address Register1972.12.17 DMILE2D—DMI Link Entry 2 Description Register1982.12.18 DMILE2A—DMI Link Entry 2 Address Register1982.12.19 LCAP—Link Capabilities Register1992.12.20 LCTL—Link Control Register2002.12.21 LSTS—DMI Link Status Register2012.12.22 LCTL2—Link Control 2 Register2022.12.23 LSTS2—Link Status 2 Register2042.12.24 AFE_BMUF0—AFE BMU Configuration Function 0 Register2042.12.25 AFE_BMUT0—AFE BMU Configuration Test 0 Register2042.13 MCHBAR Registers in Memory Controller – Channel 02052.13.1 TC_DBP_C0—Timing of DDR Bin Parameters Register2052.13.2 TC_RAP_C0—Timing of DDR Regular Access Parameters Register2062.13.3 SC_IO_LATENCY_C0—IO Latency Configuration Register2062.13.4 TC_SRFTP_C0—Self-Refresh Timing Parameters Register2072.13.5 PM_PDWN_config_C0—Power-down Configuration Register2072.13.6 TC_RFP_C0—Refresh Parameters Register2082.13.7 TC_RFTP_C0—Refresh Timing Parameters Register2082.14 MCHBAR Registers in Memory Controller – Channel 12092.14.1 TC_DBP_C1—Timing of DDR Bin Parameters Register2092.14.2 TC_RAP_C1—Timing of DDR Regular Access Parameters Register2102.14.3 SC_IO_LATENCY_C1—IO Latency Configuration Register2102.14.4 TC_SRFTP_C1—Self-Refresh Timing Parameters Register2112.14.5 PM_PDWN_Config_C1—Power-down Configuration Register2112.14.6 TC_RFP_C1—Refresh Parameters Register2122.14.7 TC_RFTP_C1—Refresh Timing Parameters Register2122.15 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub (IMPH)2132.15.1 CRDTCTL3—Credit Control 3 Register2132.16 MCHBAR Registers in Memory Controller – Common2142.16.1 MAD_CHNL—Address Decoder Channel Configuration Register2142.16.2 MAD_DIMM_ch0—Address Decode Channel 0 Register2152.16.3 MAD_DIMM_ch1—Address Decode Channel 1 Register2162.16.4 PM_SREF_config—Self Refresh Configuration Register2172.17 Memory Controller MMIO Registers Broadcast Group2182.17.1 PM_PDWN_Config—Power-down Configuration Register2182.17.2 PM_CMD_PWR—Power Management Command Power Register2192.17.3 PM_BW_LIMIT_config—BW Limit Configuration Register2192.18 Integrated Graphics VT-d Remapping Engine Registers2202.18.1 VER_REG—Version Register2212.18.2 CAP_REG—Capability Register2222.18.3 ECAP_REG—Extended Capability Register2252.18.4 GCMD_REG—Global Command Register2262.18.5 GSTS_REG—Global Status Register2302.18.6 RTADDR_REG—Root-Entry Table Address Register2312.18.7 CCMD_REG—Context Command Register2322.18.8 FSTS_REG—Fault Status Register2342.18.9 FECTL_REG—Fault Event Control Register2362.18.10 FEDATA_REG—Fault Event Data Register2372.18.11 FEADDR_REG—Fault Event Address Register2372.18.12 FEUADDR_REG—Fault Event Upper Address Register2372.18.13 AFLOG_REG—Advanced Fault Log Register2382.18.14 PMEN_REG—Protected Memory Enable Register2392.18.15 PLMBASE_REG—Protected Low-Memory Base Register2402.18.16 PLMLIMIT_REG—Protected Low-Memory Limit Register2412.18.17 PHMBASE_REG—Protected High-Memory Base Register2422.18.18 PHMLIMIT_REG—Protected High-Memory Limit Register2432.18.19 IQH_REG—Invalidation Queue Head Register2442.18.20 IQT_REG—Invalidation Queue Tail Register2442.18.21 IQA_REG—Invalidation Queue Address Register2452.18.22 ICS_REG—Invalidation Completion Status Register2452.18.23 IECTL_REG—Invalidation Event Control Register2462.18.24 IEDATA_REG—Invalidation Event Data Register2472.18.25 IEUADDR_REG—Invalidation Event Upper Address Register2472.18.26 IRTA_REG—Interrupt Remapping Table Address Register2482.18.27 IVA_REG—Invalidate Address Register2492.18.28 IOTLB_REG—IOTLB Invalidate Register2502.18.29 FRCDL_REG—Fault Recording Low Register2522.18.30 FRCDH_REG—Fault Recording High Register2532.18.31 VTPOLICY—DMA Remap Engine Policy Control Register2542.19 PCU MCHBAR Registers2552.19.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Configuration Register2562.19.2 MEM_TRML_THRESHOLDS_CONFIG—Memory Thermal Thresholds Configuration Register2572.19.3 MEM_TRML_STATUS_REPORT—Memory Thermal Status Report Register2582.19.4 MEM_TRML_TEMPERATURE_REPORT—Memory Thermal Temperature Report Register2592.19.5 MEM_TRML_INTERRUPT—Memory Thermal Interrupt Register2592.19.6 GT_PERF_STATUS—GT Performance Status Register2602.19.7 RP_STATE_CAP—RP State Capability Register2602.19.8 SSKPD—Sticky Scratchpad Data Register2612.20 PXPEPBAR Registers2632.20.1 EPVC0RCTL—EP VC 0 Resource Control Register2632.21 Default PEG/DMI VT-d Remapping Engine Registers2642.21.1 VER_REG—Version Register2652.21.2 CAP_REG—Capability Register2662.21.3 ECAP_REG—Extended Capability Register2692.21.4 GCMD_REG—Global Command Register2702.21.5 GSTS_REG—Global Status Register2742.21.6 RTADDR_REG—Root-Entry Table Address Register2752.21.7 CCMD_REG—Context Command Register2762.21.8 FSTS_REG—Fault Status Register2782.21.9 FECTL_REG—Fault Event Control Register2802.21.10 FEDATA_REG—Fault Event Data Register2812.21.11 FEADDR_REG—Fault Event Address Register2812.21.12 FEUADDR_REG—Fault Event Upper Address Register2812.21.13 AFLOG_REG—Advanced Fault Log Register2822.21.14 PMEN_REG—Protected Memory Enable Register2832.21.15 PLMBASE_REG—Protected Low-Memory Base Register2842.21.16 PLMLIMIT_REG—Protected Low-Memory Limit Register2852.21.17 PHMBASE_REG—Protected High-Memory Base Register2862.21.18 PHMLIMIT_REG—Protected High-Memory Limit Register2872.21.19 IQH_REG—Invalidation Queue Head Register2882.21.20 EG—Invalidation Queue Tail Register2882.21.21 IQA_REG—Invalidation Queue Address Register2892.21.22 ICS_REG—Invalidation Completion Status Register2892.21.23 IECTL_REG—Invalidation Event Control Register2902.21.24 IEDATA_REG—Invalidation Event Data Register2912.21.25 IEADDR_REG—Invalidation Event Address Register2912.21.26 IEUADDR_REG—Invalidation Event Upper Address Register2922.21.27 IRTA_REG—Interrupt Remapping Table Address Register2922.21.28 IVA_REG—Invalidate Address Register2932.21.29 IOTLB_REG—IOTLB Invalidate Register294Tamaño: 2 MBPáginas: 296Language: EnglishManuales abiertas
