Intel Intel Core2 Extreme QX6850 Manuales de usuario

Tabla de contenidos

• Contents

  3
  • Figures

    5
  • Tables

    5
• Intel® Core™2 Extreme Quad-Core Processor QX6800 Features

  6
• Revision History

  7
• Intel® Core™2 Extreme Quad-Core Processor QX6800D

  1
• 1 Introduction

  9
  • 1.1 Terminology

    9
    • 1.1.1 Processor Packaging Terminology

      10
  • 1.2 References

    11
• 2 Electrical Specifications

  13
  • 2.1 Power and Ground Lands

    13
  • 2.2 Decoupling Guidelines

    13
    • 2.2.1 VCC Decoupling

      13
    • 2.2.2 VTT Decoupling

      13
  • 2.3 Voltage Identification

    14
  • 2.4 Reserved, Unused, and TESTHI Signals

    16
  • 2.5 Voltage and Current Specification

    17
    • 2.5.1 Absolute Maximum and Minimum Ratings

      17
    • 2.5.2 DC Voltage and Current Specification

      18
    • 2.5.3 VCCOvershoot

      20
    • 2.5.4 Die Voltage Validation

      21
  • 2.6 Signaling Specifications

    21
    • 2.6.1 FSB Signal Groups

      22
    • 2.6.2 CMOS and Open Drain Signals

      23
    • 2.6.3 Processor DC Specifications

      23
  • 2.7 Clock Specifications

    26
    • 2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

      26
    • 2.7.2 FSB Frequency Select Signals (BSEL[2:0])

      27
    • 2.7.3 Phase Lock Loop (PLL) and Filter

      27
    • 2.7.4 BCLK[1:0] Specifications

      28
  • 2.8 PECI DC Specifications

    29
• 3 Package Mechanical Specifications

  31
  • 3.1 Package Mechanical Drawing

    31
  • 3.2 Processor Component Keep-Out Zones

    35
  • 3.3 Package Loading Specifications

    35
  • 3.4 Package Handling Guidelines

    35
  • 3.5 Package Insertion Specifications

    36
  • 3.6 Processor Mass Specification

    36
  • 3.7 Processor Materials

    36
  • 3.8 Processor Markings

    36
  • 3.9 Processor Land Coordinates

    37
• 4 Land Listing and Signal Descriptions

  39
  • 4.1 Processor Land Assignments

    39
  • 4.2 Alphabetical Signals Reference

    62
• 5 Thermal Specifications and Design Considerations

  71
  • 5.1 Processor Thermal Specifications

    71
    • 5.1.1 Thermal Specifications

      71
    • 5.1.2 Thermal Metrology

      75
  • 5.2 Processor Thermal Features

    75
    • 5.2.1 Thermal Monitor

      75
    • 5.2.2 Thermal Monitor 2

      76
    • 5.2.3 On-Demand Mode

      77
    • 5.2.4 PROCHOT# Signal

      78
    • 5.2.5 THERMTRIP# Signal

      78
  • 5.3 Platform Environment Control Interface (PECI)

    79
    • 5.3.1 Introduction

      79
    • 5.3.2 PECI Specifications

      80
• 6 Features

  81
  • 6.1 Power-On Configuration Options

    81
  • 6.2 Clock Control and Low Power States

    81
    • 6.2.1 Normal State

      82
    • 6.2.2 HALT and Extended HALT Powerdown States

      82
    • 6.2.3 Stop Grant State

      83
    • 6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State

      84
• 7 Boxed Processor Specifications

  85
• 8 Debug Tools Specifications

  87
  • 8.1 Logic Analyzer Interface (LAI)

    87
    • 8.1.1 Mechanical Considerations

      87
    • 8.1.2 Electrical Considerations

      87