Manual De Usuario (JM80547PG0961M)Tabla de contenidos1.0 Introduction71.1 Terminology81.1.1 Processor Packaging Terminology81.2 References9Table 1. References92.0 Electrical Specifications112.1 System Bus and GTLREF112.2 Power and Ground Pins112.3 Decoupling Guidelines112.3.1 VCC Decoupling122.3.2 System Bus AGTL+ Decoupling122.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking122.4 Voltage Identification12Table 2. Voltage Identification Definition132.4.1 Phase Lock Loop (PLL) Power and Filter13Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution14Figure 2. Phase Lock Loop (PLL) Filter Requirements152.5 Reserved, Unused Pins, and TESTHI[10:0]152.6 System Bus Signal Groups16Table 3. System Bus Pin Groups (Page 1 of 2)162.7 Asynchronous GTL+ Signals172.8 Test Access Port (TAP) Connection172.9 Maximum Ratings18Table 4. Processor DC Absolute Maximum Ratings182.10 Processor DC Specifications18Table 5. Voltage and Current Specifications19Table 6. System Bus Differential BCLK Specifications20Table 7. AGTL+ Signal Group DC Specifications20Table 8. Asynchronous GTL+ and TAP Signal Group DC Specifications212.11 AGTL+ System Bus Specifications21Table 9. AGTL+ Bus Voltage Definitions212.12 System Bus AC Specifications22Table 10. System Bus Differential Clock Specifications22Table 11. System Bus Common Clock AC Specifications23Table 12. System Bus Source Synch AC Specifications AGTL+ Signal Group23Table 13. Asynchronous GTL+ Signals AC Specifications24Table 14. System Bus AC Specifications (Reset Conditions)24Table 15. TAP Signals AC Specifications252.13 Processor AC Timing Waveforms25Figure 3. AC Test Circuit26Figure 4. TCK Clock Waveform26Figure 5. Differential Clock Waveform27Figure 6. System Bus Common Clock Valid Delay Timings27Figure 7. System Bus Reset and Configuration Timings28Figure 8. Source Synchronous 2X (Address) Timings28Figure 9. Source Synchronous 4X Timings29Figure 10. Power-On Reset and Configuration Timings29Figure 11. Test Reset Timings303.0 System Bus Signal Quality Specifications313.1 BCLK Signal Quality Specifications and Measurement Guidelines31Table 16. BCLK Signal Quality Specifications31Figure 12. BCLK[1:0] Signal Integrity Waveform323.2 System Bus Signal Quality Specifications and Measurement Guidelines32Table 17. Ringback Specifications for AGTL+, Asynchronous GTL+, and TAP Signal Groups32Figure 13. Low-to-High System Bus Receiver Ringback Tolerance33Figure 14. High-to-Low System Bus Receiver Ringback Tolerance333.3 System Bus Signal Quality Specifications and Measurement Guidelines333.3.1 Overshoot/Undershoot Guidelines333.3.2 Overshoot/Undershoot Magnitude343.3.3 Overshoot/Undershoot Pulse Duration343.3.4 Activity Factor343.3.5 Reading Overshoot/Undershoot Specification Tables353.3.6 Determining if a System Meets the Over/Undershoot Specifications35Table 18. Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Pro...37Table 19. Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Pro...37Table 20. Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Processors)38Table 21. Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance (1.7V Processors)38Table 22. Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Pr...39Table 23. Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Pr...39Table 24. Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Processors)40Table 25. Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance (1.75V Processors)40Figure 15. Maximum Acceptable Overshoot/Undershoot Waveform414.0 Package Mechanical Specifications43Figure 16. Exploded View of Processor Components on a System Board43Figure 17. Processor Package44Table 26. Description Table for Processor Dimensions45Figure 18. Processor Cross-Section and Keep-in45Figure 19. Processor Pin Detail46Figure 20. IHS Flatness Specification464.1 Package Load Specifications46Table 27. Package Dynamic and Static Load Specifications474.2 Processor Insertion Specifications474.3 Processor Mass Specifications47Table 28. Processor Mass474.4 Processor Materials47Table 29. Processor Material Properties484.5 Processor Markings48Figure 21. Processor Markings484.6 Processor Pin-Out Coordinates48Figure 22. Processor Pinout Diagram - Bottom View49Table 30. Pin Listing by Pin Name51Table 31. Pin Listing by Pin Number575.0 Pin Listing and Signal Definitions515.1 Processor Pin Assignments515.1.1 Pin Listing by Pin Name515.1.2 Pin Listing by Pin Number575.2 Alphabetical Signals Reference63Table 32. Signal Description (Page 1 of 8)636.0 Thermal Specifications and Design Considerations71Figure 23. Example Thermal Solution (Not to scale)716.1 Thermal Specifications72Table 33. Processor Thermal Design Power726.2 Thermal Analysis736.2.1 Measurements For Thermal Specifications736.2.1.1 Processor Case Temperature Measurement73Figure 24. Guideline Locations for Case Temperature (TCASE) Thermocouple Placement73Figure 25. Technique for Measuring with 0 Degree Angle Attachment73Figure 26. Technique for Measuring with 90 Degree Angle Attachment747.0 Features757.1 Power-On Configuration Options75Table 34. Power-On Configuration Option Pins757.2 Clock Control and Low Power States757.2.1 Normal State—State 1757.2.2 AutoHALT Powerdown State—State 275Figure 27. Stop Clock State Machine767.2.3 Stop-Grant State—State 3767.2.4 HALT/Grant Snoop State—State 4777.2.5 Sleep State—State 5777.2.6 Deep Sleep State—State 6787.3 Thermal Monitor787.3.1 Thermal Diode79Table 35. Thermal Diode Parameters79Table 36. Thermal Diode Interface808.0 Boxed Processor Specifications818.1 Introduction81Figure 28. Mechanical Representation of the Boxed Pentium 4 Processor818.2 Mechanical Specifications818.2.1 Boxed Processor Fan Heatsink Dimensions82Figure 29. Side View Space Requirements for the Boxed Processor82Figure 30. Top View Space Requirements for the Boxed Processor838.2.2 Boxed Processor Fan Heatsink Weight838.2.3 Boxed Processor Retention Mechanism and Fan Heatsink Supports838.3 Boxed Processor Requirements848.3.1 Fan Heatsink Power Supply84Figure 31. Boxed Processor Fan Heatsink Power Cable Connector Description84Table 37. Fan Heatsink Power and Signal Specifications84Figure 32. Acceptable System Board Power Header Placement Relative to Processor Socket858.4 Thermal Specifications858.4.1 Boxed Processor Cooling Requirements85Figure 33. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)86Figure 34. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)868.4.2 Variable Speed Fan87Figure 35. Boxed Processor Fan Heatsink Set Points87Table 38. Boxed Processor Fan Heatsink Set Points879.0 Debug Tools Specifications899.1 Logic Analyzer Interface (LAI)899.1.1 Mechanical Considerations899.1.2 Electrical Considerations89Tamaño: 2 MBPáginas: 90Language: EnglishManuales abiertas
Manual De Usuario (JM80547PG0961MM)Tabla de contenidos1.0 Introduction71.1 Terminology81.1.1 Processor Packaging Terminology81.2 References9Table 1. References92.0 Electrical Specifications112.1 System Bus and GTLREF112.2 Power and Ground Pins112.3 Decoupling Guidelines112.3.1 VCC Decoupling122.3.2 System Bus AGTL+ Decoupling122.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking122.4 Voltage Identification12Table 2. Voltage Identification Definition132.4.1 Phase Lock Loop (PLL) Power and Filter13Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution14Figure 2. Phase Lock Loop (PLL) Filter Requirements152.5 Reserved, Unused Pins, and TESTHI[10:0]152.6 System Bus Signal Groups16Table 3. System Bus Pin Groups (Page 1 of 2)162.7 Asynchronous GTL+ Signals172.8 Test Access Port (TAP) Connection172.9 Maximum Ratings18Table 4. Processor DC Absolute Maximum Ratings182.10 Processor DC Specifications18Table 5. Voltage and Current Specifications19Table 6. System Bus Differential BCLK Specifications20Table 7. AGTL+ Signal Group DC Specifications20Table 8. Asynchronous GTL+ and TAP Signal Group DC Specifications212.11 AGTL+ System Bus Specifications21Table 9. AGTL+ Bus Voltage Definitions212.12 System Bus AC Specifications22Table 10. System Bus Differential Clock Specifications22Table 11. System Bus Common Clock AC Specifications23Table 12. System Bus Source Synch AC Specifications AGTL+ Signal Group23Table 13. Asynchronous GTL+ Signals AC Specifications24Table 14. System Bus AC Specifications (Reset Conditions)24Table 15. TAP Signals AC Specifications252.13 Processor AC Timing Waveforms25Figure 3. AC Test Circuit26Figure 4. TCK Clock Waveform26Figure 5. Differential Clock Waveform27Figure 6. System Bus Common Clock Valid Delay Timings27Figure 7. System Bus Reset and Configuration Timings28Figure 8. Source Synchronous 2X (Address) Timings28Figure 9. Source Synchronous 4X Timings29Figure 10. Power-On Reset and Configuration Timings29Figure 11. Test Reset Timings303.0 System Bus Signal Quality Specifications313.1 BCLK Signal Quality Specifications and Measurement Guidelines31Table 16. BCLK Signal Quality Specifications31Figure 12. BCLK[1:0] Signal Integrity Waveform323.2 System Bus Signal Quality Specifications and Measurement Guidelines32Table 17. Ringback Specifications for AGTL+, Asynchronous GTL+, and TAP Signal Groups32Figure 13. Low-to-High System Bus Receiver Ringback Tolerance33Figure 14. High-to-Low System Bus Receiver Ringback Tolerance333.3 System Bus Signal Quality Specifications and Measurement Guidelines333.3.1 Overshoot/Undershoot Guidelines333.3.2 Overshoot/Undershoot Magnitude343.3.3 Overshoot/Undershoot Pulse Duration343.3.4 Activity Factor343.3.5 Reading Overshoot/Undershoot Specification Tables353.3.6 Determining if a System Meets the Over/Undershoot Specifications35Table 18. Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Pro...37Table 19. Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Pro...37Table 20. Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.7V Processors)38Table 21. Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance (1.7V Processors)38Table 22. Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Pr...39Table 23. Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Pr...39Table 24. Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (1.75V Processors)40Table 25. Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance (1.75V Processors)40Figure 15. Maximum Acceptable Overshoot/Undershoot Waveform414.0 Package Mechanical Specifications43Figure 16. Exploded View of Processor Components on a System Board43Figure 17. Processor Package44Table 26. Description Table for Processor Dimensions45Figure 18. Processor Cross-Section and Keep-in45Figure 19. Processor Pin Detail46Figure 20. IHS Flatness Specification464.1 Package Load Specifications46Table 27. Package Dynamic and Static Load Specifications474.2 Processor Insertion Specifications474.3 Processor Mass Specifications47Table 28. Processor Mass474.4 Processor Materials47Table 29. Processor Material Properties484.5 Processor Markings48Figure 21. Processor Markings484.6 Processor Pin-Out Coordinates48Figure 22. Processor Pinout Diagram - Bottom View49Table 30. Pin Listing by Pin Name51Table 31. Pin Listing by Pin Number575.0 Pin Listing and Signal Definitions515.1 Processor Pin Assignments515.1.1 Pin Listing by Pin Name515.1.2 Pin Listing by Pin Number575.2 Alphabetical Signals Reference63Table 32. Signal Description (Page 1 of 8)636.0 Thermal Specifications and Design Considerations71Figure 23. Example Thermal Solution (Not to scale)716.1 Thermal Specifications72Table 33. Processor Thermal Design Power726.2 Thermal Analysis736.2.1 Measurements For Thermal Specifications736.2.1.1 Processor Case Temperature Measurement73Figure 24. Guideline Locations for Case Temperature (TCASE) Thermocouple Placement73Figure 25. Technique for Measuring with 0 Degree Angle Attachment73Figure 26. Technique for Measuring with 90 Degree Angle Attachment747.0 Features757.1 Power-On Configuration Options75Table 34. Power-On Configuration Option Pins757.2 Clock Control and Low Power States757.2.1 Normal State—State 1757.2.2 AutoHALT Powerdown State—State 275Figure 27. Stop Clock State Machine767.2.3 Stop-Grant State—State 3767.2.4 HALT/Grant Snoop State—State 4777.2.5 Sleep State—State 5777.2.6 Deep Sleep State—State 6787.3 Thermal Monitor787.3.1 Thermal Diode79Table 35. Thermal Diode Parameters79Table 36. Thermal Diode Interface808.0 Boxed Processor Specifications818.1 Introduction81Figure 28. Mechanical Representation of the Boxed Pentium 4 Processor818.2 Mechanical Specifications818.2.1 Boxed Processor Fan Heatsink Dimensions82Figure 29. Side View Space Requirements for the Boxed Processor82Figure 30. Top View Space Requirements for the Boxed Processor838.2.2 Boxed Processor Fan Heatsink Weight838.2.3 Boxed Processor Retention Mechanism and Fan Heatsink Supports838.3 Boxed Processor Requirements848.3.1 Fan Heatsink Power Supply84Figure 31. Boxed Processor Fan Heatsink Power Cable Connector Description84Table 37. Fan Heatsink Power and Signal Specifications84Figure 32. Acceptable System Board Power Header Placement Relative to Processor Socket858.4 Thermal Specifications858.4.1 Boxed Processor Cooling Requirements85Figure 33. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)86Figure 34. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)868.4.2 Variable Speed Fan87Figure 35. Boxed Processor Fan Heatsink Set Points87Table 38. Boxed Processor Fan Heatsink Set Points879.0 Debug Tools Specifications899.1 Logic Analyzer Interface (LAI)899.1.1 Mechanical Considerations899.1.2 Electrical Considerations89Tamaño: 2 MBPáginas: 90Language: EnglishManuales abiertas
