Microchip Technology AC164112 Manuales de usuario

Tabla de contenidos

• Devices Included In This Data Sheet:

  3
• High-Performance RISC CPU:

  3
• Special Microcontroller Features:

  3
• Extreme Low-Power Management PIC16LF72X with nanoWatt XLP:

  3
• Analog Features:

  3
• Peripheral Highlights:

  3
• Pin Diagrams – 28-Pin PDIP/SOIC/SSOP/QFN/UQFN (PIC16F722/723/726/PIC16LF722/723/726)

  5
  • TABLE 1: 28-Pin PDIP/SOIC/SSOP/QFN/UQFN Summary (PIC16F722/723/726/PIC16LF722/723/726)

    6
• Pin Diagrams – 40-Pin PDIP (PIC16F724/727/PIC16LF724/727)

  7
• Pin Diagrams – 44-Pin TQFP (PIC16F724/727/PIC16LF724/727)

  8
• Pin Diagrams – 44-Pin QFN (PIC16F724/727/PIC16LF724/727)

  9
  • TABLE 2: 40/44-Pin PDIP/tqfp/qfn Summary (PIC16F724/727/PIC16LF724/727)

    10
• Most Current Data Sheet

  12
• Errata

  12
• Customer Notification System

  12
• 1.0 Device Overview

  13
  • FIGURE 1-1: PIC16F722/723/726/PIC16LF722/723/726 Block Diagram

    14
  • FIGURE 1-2: PIC16F724/727/PIC16LF724/727 Block Diagram

    15
  • TABLE 1-1: PIC16F72X/PIC16LF72X Pinout Description

    16
• 2.0 Memory Organization

  19
  • 2.1 Program Memory Organization

    19
    • FIGURE 2-1: Program Memory Map And Stack For The PIC16F722/LF722

      19
    • FIGURE 2-2: Program Memory Map And Stack For The PIC16F723/LF723 and PIC16F724/LF724

      19
    • FIGURE 2-3: Program Memory Map And Stack For The PIC16F726/LF726 and PIC16F727/LF727

      20
  • 2.2 Data Memory Organization

    20
    • 2.2.1 General Purpose Register File

      20
    • 2.2.2 Special FUNCTION Registers

      20
      • FIGURE 2-4: PIC16F722/LF722 Special Function Registers

        21
      • FIGURE 2-5: PIC16F723/LF723 and PIC16F724/LF724 Special Function Registers

        22
      • FIGURE 2-6: PIC16F726/LF726 and PIC16F727/LF727 Special Function Registers

        23
      • TABLE 2-1: PIC16F72X/PIC16LF72X Special Function Register Summary

        24
      • Register 2-1: STATUS: STATUS Register

        27
      • Register 2-2: OPTION_REG: OPTION Register

        28
      • Register 2-3: PCON: Power Control Register

        29
  • 2.3 PCL and PCLATH

    30
    • FIGURE 2-7: Loading Of PC In Different Situations

      30
    • 2.3.1 computed goto

      30
    • 2.3.2 Stack

      30
  • 2.4 Program Memory Paging

    30
    • EXAMPLE 2-1: Call of a Subroutine in Page 1 from Page 0

      30
  • 2.5 Indirect Addressing, INDF and FSR Registers

    31
    • EXAMPLE 2-2: Indirect Addressing

      31
    • FIGURE 2-8: Direct/Indirect Addressing

      31
• 3.0 Resets

  33
  • FIGURE 3-1: Simplified Block Diagram Of On-Chip Reset Circuit

    33
  • 3.1 MCLR

    35
    • FIGURE 3-2: Recommended MCLR Circuit

      35
  • 3.2 Power-on Reset (POR)

    35
  • 3.3 Power-up Timer (PWRT)

    35
  • 3.4 Watchdog Timer (WDT)

    35
    • 3.4.1 WDT Oscillator

      35
    • 3.4.2 WDT Control

      36
      • TABLE 3-1: WDT Status

        36
  • 3.5 Brown-Out Reset (BOR)

    37
    • FIGURE 3-3: Brown-Out Situations

      37
  • 3.6 Time-out Sequence

    38
  • 3.7 Power Control (PCON) Register

    38
    • TABLE 3-2: Time-Out In Various Situations

      38
    • TABLE 3-3: Reset Bits And Their Significance

      38
    • FIGURE 3-4: Time-Out Sequence On Power-Up (Delayed MCLR): Case 1

      39
    • FIGURE 3-5: Time-Out Sequence On Power-Up (Delayed MCLR): Case 2

      39
    • FIGURE 3-6: Time-Out Sequence On Power-Up (MCLR With Vdd): Case 3

      39
    • TABLE 3-4: Initialization Condition for Registers

      40
    • TABLE 3-5: Initialization Condition For Special Registers

      42
    • TABLE 3-6: Summary Of Registers Associated With Resets

      42
• 4.0 Interrupts

  43
  • FIGURE 4-1: Interrupt Logic

    43
  • 4.1 Operation

    44
  • 4.2 Interrupt Latency

    44
    • FIGURE 4-2: INT Pin Interrupt Timing

      44
  • 4.3 Interrupts During Sleep

    45
  • 4.4 INT Pin

    45
  • 4.5 Context Saving

    45
    • EXAMPLE 4-1: Saving W, STATUS and PCLATH Registers in RAM

      45
    • 4.5.1 INTCON Register

      46
      • Register 4-1: INTCON: Interrupt Control Register

        46
    • 4.5.2 PIE1 Register

      47
      • Register 4-2: PIE1: Peripheral Interrupt Enable Register 1

        47
    • 4.5.3 PIE2 Register

      48
      • Register 4-3: PIE2: Peripheral Interrupt Enable Register 2

        48
    • 4.5.4 PIR1 Register

      49
      • Register 4-4: PIR1: Peripheral Interrupt Request Register 1

        49
    • 4.5.5 PIR2 Register

      50
      • Register 4-5: PIR2: Peripheral Interrupt Request Register 2

        50
      • TABLE 4-1: Summary of Registers Associated with Interrupts

        50
• 5.0 Low Dropout (LDO) Voltage Regulator

  51
• 6.0 I/O Ports

  53
  • 6.1 Alternate Pin Function

    53
    • Register 6-1: APFCON: Alternate Pin Function COntrol Register

      53
  • 6.2 PORTA and the TRISA Registers

    54
    • EXAMPLE 6-1: Initializing PORTA

      54
    • Register 6-2: PORTA: PORTA Register

      54
    • Register 6-3: TRISA: PORTA Tri-State Register

      54
    • 6.2.1 ANSELA Register

      55
      • Register 6-4: ANSELA: PORTA Analog Select Register

        55
    • 6.2.2 Pin Descriptions and Diagrams

      56
      • FIGURE 6-1: Block Diagram of RA0

        57
      • FIGURE 6-2: RA<3:1> Block Diagram

        58
      • FIGURE 6-3: Block Diagram of RA4

        58
      • FIGURE 6-4: Block Diagram of RA5

        59
      • FIGURE 6-5: Block Diagram of RA6

        60
      • FIGURE 6-6: Block Diagram of RA7

        60
      • TABLE 6-1: Summary of Registers Associated with PORTA

        61
  • 6.3 PORTB and TRISB Registers

    62
    • EXAMPLE 6-2: Initializing PORTB

      62
    • 6.3.1 ANSELB Register

      62
    • 6.3.2 Weak Pull-Ups

      62
    • 6.3.3 Interrupt-on-Change

      62
      • Register 6-5: PORTB: PORTB Register

        63
      • Register 6-6: TRISB: PORTB Tri-State Register

        63
      • Register 6-7: WPUB: WEAK PULL-uP PORTB REGISTER

        64
      • Register 6-8: IOCB: Interrupt-on-change PORTB Register

        64
      • Register 6-9: ANSELB: PORTB Analog Select Register

        64
    • 6.3.4 Pin Descriptions and Diagrams

      65
      • FIGURE 6-7: Block Diagram of RB0

        66
      • FIGURE 6-8: Block Diagram of RB4, RB<2:1>

        67
      • FIGURE 6-9: Block Diagram of RB3

        68
      • FIGURE 6-10: Block Diagram of rb5

        69
      • FIGURE 6-11: Block Diagram of RB6

        70
      • FIGURE 6-12: Block Diagram of RB7

        71
      • TABLE 6-2: Summary of Registers Associated with PORTB

        72
  • 6.4 PORTC and TRISC Registers

    73
    • EXAMPLE 6-3: Initializing PORTC

      73
    • Register 6-10: PORTC: PORTC Register

      73
    • Register 6-11: TRISC: PORTC Tri-State Register

      73
    • 6.4.1 RC0/T1OSO/T1CKI

      74
    • 6.4.2 RC1/T1OSi/CCP2

      74
    • 6.4.3 RC2/CCP1

      74
    • 6.4.4 RC3/SCK/SCL

      74
    • 6.4.5 RC4/SDI/SDA

      74
    • 6.4.6 RC5/SDO

      74
    • 6.4.7 RC6/TX/CK

      74
    • 6.4.8 RC7/RX/DT

      74
      • FIGURE 6-13: Block Diagram of RC0

        75
      • FIGURE 6-14: Block Diagram of RC1

        75
      • FIGURE 6-15: Block Diagram of RC2

        76
      • FIGURE 6-16: Block Diagram of RC3

        76
      • FIGURE 6-17: Block Diagram of RC4

        77
      • FIGURE 6-18: Block Diagram of RC5

        77
      • FIGURE 6-19: Block Diagram of RC6

        78
      • FIGURE 6-20: Block Diagram of RC7

        78
      • TABLE 6-3: Summary of Registers Associated with PORTC

        79
  • 6.5 PORTD and TRISD Registers

    80
    • EXAMPLE 6-4: Initializing PORTD

      80
    • 6.5.1 ANSELD Register

      80
      • Register 6-12: PORTD: PORTD Register(1)

        80
      • Register 6-13: TRISD: PORTD Tri-State Register(1)

        81
      • Register 6-14: ANSELD: PORTD Analog Select Register(2)

        81
    • 6.5.2 RD0/CPS8

      82
    • 6.5.3 RD1/CPS9

      82
    • 6.5.4 RD2/CPS10

      82
    • 6.5.5 RD3/CPS11

      82
    • 6.5.6 RD4/CPS12

      82
    • 6.5.7 RD5/CPS13

      82
    • 6.5.8 RD6/CPS14

      82
    • 6.5.9 RD7/CPS15

      82
      • FIGURE 6-21: Block Diagram of RD<7:0>

        82
      • TABLE 6-4: Summary of Registers Associated with PORTD(1)

        83
  • 6.6 PORTE and TRISE Registers

    84
    • EXAMPLE 6-5: Initializing PORTE

      84
    • Register 6-15: PORTE: PORTE Register

      85
    • Register 6-16: TRISE: PORTE Tri-State Register

      85
    • Register 6-17: ANSELE: PORTE Analog Select Register

      86
    • TABLE 6-5: Summary of Registers Associated with PORTE

      86
    • 6.6.1 RE0/AN5(1)

      87
    • 6.6.2 RE1/AN6(1)

      87
    • 6.6.3 RE2/AN7(1)

      87
    • 6.6.4 RE3/MCLR/Vpp

      87
      • FIGURE 6-22: Block Diagram of RE<2:0>

        88
      • FIGURE 6-23: Block Diagram of RE3

        88
• 7.0 Oscillator Module

  89
  • 7.1 Overview

    89
    • FIGURE 7-1: Simplified PIC® MCU Clock Source Block Diagram

      89
  • 7.2 Clock Source Modes

    90
  • 7.3 Internal Clock Modes

    90
    • 7.3.1 INTOSC and INTOSCIO Modes

      90
    • 7.3.2 Frequency Select Bits (IRCF)

      90
  • 7.4 Oscillator Control

    91
    • Register 7-1: OSCCON: Oscillator Control Register

      91
  • 7.5 Oscillator Tuning

    92
    • Register 7-2: OSCTUNE: Oscillator Tuning ReGister

      92
  • 7.6 External Clock Modes

    93
    • 7.6.1 Oscillator Start-up Timer (OST)

      93
    • 7.6.2 EC Mode

      93
      • FIGURE 7-2: External Clock (EC) Mode Operation

        93
    • 7.6.3 LP, XT, HS Modes

      93
      • FIGURE 7-3: Quartz Crystal Operation (LP, XT or HS Mode)

        93
      • FIGURE 7-4: Ceramic Resonator Operation (XT or HS Mode)

        94
    • 7.6.4 External RC Modes

      94
      • FIGURE 7-5: External RC Modes

        94
      • TABLE 7-1: Summary of Registers Associated with Clock Sources

        94
• 8.0 Device Configuration

  95
  • 8.1 Configuration Words

    95
    • Register 8-1: CONFIG1: Configuration Word Register 1

      95
    • Register 8-2: CONFIG2: Configuration Word Register 2

      96
  • 8.2 Code Protection

    97
  • 8.3 User ID

    97
• 9.0 Analog-to-Digital Converter (ADC) Module

  99
  • FIGURE 9-1: ADC Block Diagram

    99
  • 9.1 ADC Configuration

    100
    • 9.1.1 Port Configuration

      100
    • 9.1.2 Channel Selection

      100
    • 9.1.3 ADC Voltage Reference

      100
    • 9.1.4 Conversion Clock

      100
      • TABLE 9-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies

        101
      • FIGURE 9-2: Analog-to-Digital Conversion Tad Cycles

        101
    • 9.1.5 Interrupts

      102
  • 9.2 ADC Operation

    102
    • 9.2.1 Starting a Conversion

      102
    • 9.2.2 Completion of a Conversion

      102
    • 9.2.3 Terminating a conversion

      102
    • 9.2.4 ADC Operation During Sleep

      102
    • 9.2.5 Special Event Trigger

      102
    • 9.2.6 A/D Conversion Procedure

      103
      • EXAMPLE 9-1: A/D Conversion

        103
    • 9.2.7 ADC Register Definitions

      104
      • Register 9-1: ADCON0: A/D Control Register 0

        104
      • Register 9-2: ADCON1: A/D Control Register 1

        105
      • Register 9-3: ADRES: ADC Result Register

        105
  • 9.3 A/D Acquisition Requirements

    106
    • EQUATION 9-1: Acquisition Time Example

      106
    • FIGURE 9-3: Analog Input Model

      107
    • FIGURE 9-4: ADC Transfer Function

      107
    • TABLE 9-2: Summary of Associated ADC Registers

      108
• 10.0 Fixed Voltage Reference

  109
  • Register 10-1: FVRCON: Fixed Voltage Reference Register

    109
• 11.0 Timer0 Module

  111
  • 11.1 Timer0 Operation

    111
    • 11.1.1 8-bit Timer mode

      111
    • 11.1.2 8-Bit Counter Mode

      111
      • FIGURE 11-1: Block Diagram of the Timer0/WDT Prescaler

        111
    • 11.1.3 Software Programmable Prescaler

      112
    • 11.1.4 Timer0 Interrupt

      112
    • 11.1.5 8-BIT COUNTER MODE SYNCHRONIZATION

      112
      • Register 11-1: OPTION_REG: OPTION Register

        113
      • TABLE 11-1: Summary of Registers Associated with Timer0

        113
• 12.0 Timer1 Module with Gate Control

  115
  • FIGURE 12-1: Timer1 Block Diagram

    115
  • 12.1 Timer1 Operation

    116
    • TABLE 12-1: Timer1 Enable Selections

      116
  • 12.2 Clock Source Selection

    116
    • 12.2.1 Internal Clock Source

      116
    • 12.2.2 External Clock Source

      116
      • TABLE 12-2: Clock Source Selections

        116
  • 12.3 Timer1 Prescaler

    117
  • 12.4 Timer1 Oscillator

    117
  • 12.5 Timer1 Operation in Asynchronous Counter Mode

    117
    • 12.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode

      117
  • 12.6 Timer1 Gate

    118
    • 12.6.1 Timer1 Gate Count Enable

      118
      • TABLE 12-3: Timer1 Gate Enable Selections

        118
    • 12.6.2 Timer1 Gate Source Selection

      118
      • TABLE 12-4: Timer1 Gate Sources

        118
      • TABLE 12-5: WDT/Timer1 Gate Interaction

        119
    • 12.6.3 Timer1 Gate Toggle Mode

      119
    • 12.6.4 Timer1 Gate Single-Pulse Mode

      119
    • 12.6.5 Timer1 Gate Value Status

      119
    • 12.6.6 Timer1 Gate Event Interrupt

      119
  • 12.7 Timer1 Interrupt

    120
  • 12.8 Timer1 Operation During Sleep

    120
  • 12.9 CCP Capture/Compare Time Base

    120
  • 12.10 CCP Special Event Trigger

    120
    • FIGURE 12-2: Timer1 Incrementing Edge

      120
    • FIGURE 12-3: Timer1 Gate Count Enable Mode

      121
    • FIGURE 12-4: Timer1 Gate Toggle Mode

      121
    • FIGURE 12-5: Timer1 Gate Single-Pulse Mode

      122
    • FIGURE 12-6: Timer1 Gate Single-Pulse and Toggle Combined Mode

      123
  • 12.11 Timer1 Control Register

    124
    • Register 12-1: T1CON: Timer1 Control Register

      124
  • 12.12 Timer1 Gate Control Register

    125
    • Register 12-2: T1GCON: Timer1 Gate Control Register

      125
    • TABLE 12-6: Summary of Registers Associated with Timer1

      126
• 13.0 Timer2 Module

  127
  • 13.1 Timer2 Operation

    127
    • FIGURE 13-1: Timer2 Block Diagram

      127
    • Register 13-1: T2CON: Timer2 Control Register

      128
    • TABLE 13-1: Summary of Registers Associated With Timer2

      128
• 14.0 Capacitive Sensing Module

  129
  • FIGURE 14-1: Capacitive Sensing Block Diagram

    129
  • 14.1 Analog MUX

    130
  • 14.2 Capacitive Sensing Oscillator

    130
  • 14.3 Timer resources

    130
  • 14.4 Fixed Time Base

    130
    • 14.4.1 Timer0

      130
    • 14.4.2 Timer1

      130
      • TABLE 14-1: TIMER1 ENABLE FUNCTION

        130
  • 14.5 Software Control

    131
    • 14.5.1 Nominal Frequency (No Capacitive Load)

      131
    • 14.5.2 Reduced Frequency (additional capacitive load)

      131
    • 14.5.3 Frequency threshold

      131
  • 14.6 Operation during Sleep

    132
    • Register 14-1: CPSCON0: Capacitive Sensing Control Register 0

      133
    • Register 14-2: CPSCON1: Capacitive Sensing Control Register 1

      134
    • TABLE 14-2: Summary of Registers Associated with Capacitive Sensing

      134
• 15.0 Capture/Compare/PWM (CCP) Module

  135
  • TABLE 15-1: CCP Mode – Timer Resources Required

    135
  • TABLE 15-2: Interaction of Two CCP Modules

    135
  • Register 15-1: CCPxCON: CCPx Control Register

    136
  • 15.1 Capture Mode

    137
    • 15.1.1 CCPx pin Configuration

      137
      • FIGURE 15-1: Capture Mode Operation Block Diagram

        137
    • 15.1.2 Timer1 Mode Selection

      137
    • 15.1.3 Software Interrupt

      137
    • 15.1.4 CCP Prescaler

      137
      • EXAMPLE 15-1: Changing Between Capture Prescalers

        137
    • 15.1.5 Capture During Sleep

      137
      • TABLE 15-3: Summary of Registers Associated with Capture

        138
  • 15.2 Compare Mode

    139
    • FIGURE 15-2: Compare Mode Operation Block Diagram

      139
    • 15.2.1 CCPx Pin Configuration

      139
    • 15.2.2 timer1 Mode Selection

      139
    • 15.2.3 Software Interrupt Mode

      139
    • 15.2.4 Special Event Trigger

      139
    • 15.2.5 Compare During Sleep

      139
      • TABLE 15-4: Summary of Registers Associated with Compare

        140
  • 15.3 PWM Mode

    141
    • FIGURE 15-3: Simplified PWM Block Diagram

      141
    • FIGURE 15-4: CCP PWM Output

      141
    • 15.3.1 CCPx Pin Configuration

      141
    • 15.3.2 PWM period

      142
      • EQUATION 15-1: PWM Period

        142
    • 15.3.3 PWM Duty Cycle

      142
      • EQUATION 15-2: Pulse Width

        142
      • EQUATION 15-3: Duty Cycle Ratio

        142
    • 15.3.4 PWM Resolution

      143
      • EQUATION 15-4: PWM Resolution

        143
      • TABLE 15-5: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)

        143
      • TABLE 15-6: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)

        143
    • 15.3.5 Operation in Sleep Mode

      143
    • 15.3.6 Changes in System Clock Frequency

      143
    • 15.3.7 Effects of Reset

      143
    • 15.3.8 Setup for PWM Operation

      143
      • TABLE 15-7: Summary of Registers Associated with PWM

        144
• 16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)

  145
  • FIGURE 16-1: AUSART Transmit Block Diagram

    145
  • FIGURE 16-2: AUSART Receive Block Diagram

    146
  • 16.1 AUSART Asynchronous Mode

    147
    • 16.1.1 AUSART Asynchronous Transmitter

      147
      • FIGURE 16-3: Asynchronous Transmission

        148
      • FIGURE 16-4: Asynchronous Transmission (Back-to-Back)

        148
      • TABLE 16-1: Registers Associated with Asynchronous Transmission

        149
    • 16.1.2 AUSART Asynchronous Receiver

      150
      • FIGURE 16-5: Asynchronous Reception

        152
      • TABLE 16-2: Registers Associated with Asynchronous Reception

        153
      • Register 16-1: TXSTA: Transmit STATUS AND CONTROL REGISTER

        154
      • Register 16-2: RCSTA: Receive STATUS AND CONTROL REGISTER

        155
  • 16.2 AUSART Baud Rate Generator (BRG)

    156
    • EXAMPLE 16-1: Calculating Baud Rate Error

      156
    • TABLE 16-3: Baud Rate Formulas

      156
    • TABLE 16-4: Registers Associated with the bAUD rATE gENERATOR

      156
    • TABLE 16-5: BAUD Rates for Asynchronous Modes

      157
  • 16.3 AUSART Synchronous Mode

    159
    • 16.3.1 Synchronous Master Mode

      159
      • FIGURE 16-6: Synchronous Transmission

        160
      • FIGURE 16-7: Synchronous Transmission (Through TXEN)

        160
      • TABLE 16-6: Registers Associated with Synchronous Master Transmission

        160
      • FIGURE 16-8: Synchronous Reception (Master Mode, SREN)

        162
      • TABLE 16-7: Registers Associated with Synchronous Master Reception

        162
    • 16.3.2 Synchronous slave Mode

      163
      • TABLE 16-8: Registers Associated with Synchronous Slave Transmission

        163
      • TABLE 16-9: Registers Associated with Synchronous Slave Reception

        164
  • 16.4 AUSART Operation During Sleep

    165
    • 16.4.1 Synchronous Receive During Sleep

      165
    • 16.4.2 Synchronous Transmit During Sleep

      165
• 17.0 SSP Module Overview

  167
  • 17.1 SPI Mode

    167
    • FIGURE 17-1: Typical SPI Master/Slave Connection

      167
    • FIGURE 17-2: SPI Mode Block Diagram

      168
    • 17.1.1 Master Mode

      169
      • FIGURE 17-3: SPI Master Mode Waveform

        170
      • EXAMPLE 17-1: Loading the SSPBUF (SSPSR) Register

        170
    • 17.1.2 Slave Mode

      171
      • FIGURE 17-4: SPI Mode Waveform (Slave Mode with CKE = 0)

        172
      • FIGURE 17-5: SPI Mode Waveform (Slave Mode with CKE = 1)

        172
      • FIGURE 17-6: Slave Select Synchronization Waveform

        173
      • Register 17-1: SSPCON: Sync Serial Port Control Register (SPI Mode)

        174
      • Register 17-2: SSPSTAT: Sync Serial Port Status Register (SPI Mode)

        175
      • TABLE 17-1: Summary of Registers Associated with SPI Operation

        176
  • 17.2 I2C Mode

    177
    • FIGURE 17-7: I2C™ Mode Block Diagram

      177
    • FIGURE 17-8: Typical I2C™ Connections

      177
    • 17.2.1 Hardware Setup

      177
    • 17.2.2 Start and Stop Conditions

      178
      • FIGURE 17-9: Start and Stop Conditions

        178
    • 17.2.3 Acknowledge

      178
      • TABLE 17-2: Data Transfer Received Byte Actions

        178
    • 17.2.4 Addressing

      179
    • 17.2.5 Reception

      180
      • FIGURE 17-10: I2C™ Waveforms for Reception (7-bit Address)

        180
      • FIGURE 17-11: I2C™ Slave Mode Timing (Reception, 10-bit Address)

        181
    • 17.2.6 Transmission

      182
      • FIGURE 17-12: I2C Waveforms for Transmission (7-bit Address)

        182
      • FIGURE 17-13: I2C Slave Mode Timing (Transmission 10-bit Address)

        183
    • 17.2.7 Clock Stretching

      184
    • 17.2.8 Firmware Master Mode

      184
    • 17.2.9 Multi-Master Mode

      184
    • 17.2.10 Clock Synchronization

      185
    • 17.2.11 Sleep Operation

      185
      • FIGURE 17-14: Clock Synchronization Timing

        185
      • Register 17-3: SSPCON: Synchronous Serial Port Control Register (I2C Mode)

        186
      • Register 17-4: SSPSTAT: Synchronous Serial Port Status Register (I2C Mode)

        187
      • Register 17-5: SSPMSK: SSP Mask Register

        188
      • Register 17-6: SSPADD: SSP I2C Address Register

        188
• 18.0 Program Memory Read

  189
  • EXAMPLE 18-1: PROGRAM Memory Read

    189
  • Register 18-1: PMCON1: Program Memory Control 1 register

    190
  • Register 18-2: PMDATH: Program Memory Data High register

    190
  • Register 18-3: PMDATL: Program Memory Data Low register

    190
  • Register 18-4: PMADRH: Program Memory Address High register

    191
  • Register 18-5: PMADRL: Program Memory Address Low register

    191
  • TABLE 18-1: Summary of Registers Associated with Program Memory Read

    191
• 19.0 Power-Down Mode (Sleep)

  193
  • 19.1 Wake-up from Sleep

    193
  • 19.2 Wake-up Using Interrupts

    194
    • FIGURE 19-1: Wake-Up From Sleep Through Interrupt

      194
    • TABLE 19-1: Summary of Registers Associated with pOWER-dOWN mODE

      194
• 20.0 In-Circuit Serial Programming™ (ICSP™)

  195
  • FIGURE 20-1: Typical connection for ICSP™ programming

    195
• 21.0 Instruction Set Summary

  197
  • 21.1 Read-Modify-Write Operations

    197
    • TABLE 21-1: Opcode Field Descriptions

      197
    • FIGURE 21-1: General Format for Instructions

      197
    • TABLE 21-2: PIC16F72X/PIC16LF72X Instruction Set

      198
  • 21.2 Instruction Descriptions

    199
  • 1.0 Development Support

    207
• 23.0 Electrical Specifications

  211
  • Absolute Maximum Ratings(†)

    211
  • 23.1 DC Characteristics: PIC16F72X/PIC16LF72X-I/E (Industrial, Extended)

    212
    • FIGURE 23-1: POR and POR Rearm with Slow Rising Vdd

      213
  • 23.2 DC Characteristics: PIC16F72X/PIC16LF72X-I/E (Industrial, Extended)

    214
  • 23.3 DC Characteristics: PIC16F72X/PIC16LF72X-I/E (Power-Down)

    216
  • 23.4 DC Characteristics: PIC16F72X/PIC16LF72X-I/E

    218
  • 23.5 Thermal Considerations

    220
  • 23.6 Timing Parameter Symbology

    221
    • FIGURE 23-2: Load Conditions

      221
  • 23.7 AC Characteristics: PIC16F72X-I/E

    222
    • FIGURE 23-3: Clock Timing

      222
    • FIGURE 23-4: PIC16F72X Voltage Frequency Graph, -40°C £ Ta £ +125°C

      222
    • FIGURE 23-5: PIC16LF72X Voltage Frequency Graph, -40°C £ Ta £ +125°C

      223
    • FIGURE 23-6: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature

      223
    • TABLE 23-1: Clock Oscillator Timing Requirements

      224
    • TABLE 23-2: Oscillator Parameters

      225
    • FIGURE 23-7: CLKOUT and I/O Timing

      225
    • TABLE 23-3: CLKOUT and I/O Timing Parameters

      226
    • FIGURE 23-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

      226
    • FIGURE 23-9: Brown-Out Reset Timing and Characteristics

      227
    • TABLE 23-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-Out Reset Parameters

      228
    • FIGURE 23-10: Timer0 and Timer1 External Clock Timings

      229
    • TABLE 23-5: Timer0 and Timer1 External Clock Requirements

      229
    • FIGURE 23-11: Capture/Compare/PWM Timings (CCP)

      230
    • TABLE 23-6: Capture/Compare/PWM Requirements (CCP)

      230
    • TABLE 23-7: PIC16F72X A/D Converter (ADC) Characteristics:

      230
    • TABLE 23-8: PIC16F72X A/D Conversion Requirements

      231
    • FIGURE 23-12: PIC16F72X A/D Conversion Timing (Normal Mode)

      231
    • FIGURE 23-13: PIC16F72X A/D Conversion Timing (Sleep Mode)

      232
    • FIGURE 23-14: USART Synchronous Transmission (Master/Slave) Timing

      232
    • TABLE 23-9: USART Synchronous Transmission Requirements

      232
    • FIGURE 23-15: USART Synchronous Receive (Master/Slave) Timing

      233
    • TABLE 23-10: USART Synchronous Receive Requirements

      233
    • FIGURE 23-16: SPI Master Mode Timing (CKE = 0, SMP = 0)

      234
    • FIGURE 23-17: SPI Master Mode Timing (CKE = 1, SMP = 1)

      234
    • FIGURE 23-18: SPI Slave Mode Timing (CKE = 0)

      235
    • FIGURE 23-19: SPI Slave Mode Timing (CKE = 1)

      235
    • TABLE 23-11: SPI Mode requirements

      236
    • FIGURE 23-20: I2C™ Bus Start/Stop Bits Timing

      236
    • TABLE 23-12: I2C™ Bus Start/Stop Bits Requirements

      237
    • FIGURE 23-21: I2C™ Bus Data Timing

      237
    • TABLE 23-13: I2C™ Bus Data Requirements

      238
    • TABLE 23-14: Cap Sense Oscillator Specifications

      239
    • FIGURE 23-22: Cap Sense Oscillator

      239
• 24.0 DC and AC Characteristics Graphs and Charts

  241
  • FIGURE 24-1: PIC16F72X Maximum Idd vs. Fosc over Vdd, EC Mode, Vcap = 0.1µF

    241
  • FIGURE 24-2: PIC16LF72X Maximum Idd vs. Fosc over Vdd, EC Mode

    241
  • FIGURE 24-3: PIC16F72X Typical Idd vs. Fosc Over Vdd, EC Mode, Vcap = 0.1µF

    242
  • FIGURE 24-4: PIC16LF72X Typical Idd vs. Fosc over Vdd, EC Mode

    242
  • FIGURE 24-5: PIC16F72X Maximum Idd vs. Vdd over Fosc, EXTRC Mode, Vcap = 0.1µF

    243
  • FIGURE 24-6: PIC16LF72X Maximum Idd vs. Vdd over Fosc, EXTRC Mode

    243
  • FIGURE 24-7: PIC16F72X Typical Idd vs. Vdd over Fosc, EXTRC Mode, Vcap = 0.1µF

    244
  • FIGURE 24-8: PIC16LF72X Typical Idd vs. Vdd over Fosc, EXTRC Mode

    244
  • FIGURE 24-9: PIC16F72X maximum Idd vs. Fosc over Vdd, HS Mode, Vcap = 0.1µF

    245
  • FIGURE 24-10: PIC16LF72X Maximum Idd vs. Fosc over Vdd, HS Mode

    245
  • FIGURE 24-11: PIC16F72X Typical Idd vs. Fosc over Vdd, HS Mode, Vcap = 0.1µF

    246
  • FIGURE 24-12: PIC16LF72X Typical Idd vs. Fosc over Vdd, HS Mode

    246
  • FIGURE 24-13: PIC16F72X Maximum Idd vs. Vdd Over Fosc, XT Mode, Vcap = 0.1µF

    247
  • FIGURE 24-14: PIC16LF72X Maximum Idd vs. Vdd Over Fosc, XT Mode

    247
  • FIGURE 24-15: PIC16F72X Typical Idd vs. Vdd Over Fosc, XT Mode, Vcap = 0.1µF

    248
  • FIGURE 24-16: PIC16LF72X Typical Idd vs. Vdd over Fosc, XT Mode

    248
  • FIGURE 24-17: PIC16F72X Idd vs. Vdd, LP Mode, Vcap = 0.1µF

    249
  • FIGURE 24-18: PIC16LF72X Idd vs. Vdd, LP Mode

    249
  • FIGURE 24-19: PIC16F72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF

    250
  • FIGURE 24-20: PIC16LF72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode

    250
  • FIGURE 24-21: PIC16F72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF

    251
  • FIGURE 24-22: PIC16LF72X Maximum Idd vs. Fosc over Vdd, INTOSC Mode

    251
  • FIGURE 24-23: PIC16F72X Typical Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF

    252
  • FIGURE 24-24: PIC16LF72X Typical Idd vs. Fosc over Vdd, INTOSC Mode

    252
  • FIGURE 24-25: PIC16F72X Typical Idd vs. Fosc over Vdd, INTOSC Mode, Vcap = 0.1µF

    253
  • FIGURE 24-26: PIC16LF72X Typical Idd vs. Fosc over Vdd, INTOSC Mode

    253
  • FIGURE 24-27: PIC16F72X Maximum Base Ipd vs. Vdd, Vcap = 0.1µF

    254
  • FIGURE 24-28: PIC16LF72X Maximum Base Ipd vs. Vdd

    254
  • FIGURE 24-29: PIC16F72X typical Base Ipd vs. Vdd, Vcap = 0.1µF

    255
  • FIGURE 24-30: PIC16LF72X Typical Base Ipd vs. Vdd

    255
  • FIGURE 24-31: PIC16F72X fixed Voltage Reference Ipd vs. Vdd, Vcap = 0.1µF

    256
  • FIGURE 24-32: PIC16LF72X Fixed Voltage Reference Ipd vs. Vdd

    256
  • FIGURE 24-33: PIC16F72X BOR Ipd vs. Vdd, Vcap = 0.1µF

    257
  • FIGURE 24-34: PIC16LF72X BOR Ipd vs. Vdd

    257
  • FIGURE 24-35: PIC16F72X Cap Sense High Power Ipd vs. Vdd, Vcap = 0.1µF

    258
  • FIGURE 24-36: PIC16LF72X Cap Sense High Power Ipd vs. Vdd

    258
  • FIGURE 24-37: PIC16F72X Cap Sense Medium Power Ipd vs. Vdd, Vcap = 0.1µF

    259
  • FIGURE 24-38: PIC16LF72X cap Sense Medium Power Ipd vs. Vdd

    259
  • FIGURE 24-39: PIC16F72X Cap Sense low Power Ipd vs. Vdd, Vcap = 0.1µF

    260
  • FIGURE 24-40: PIC16LF72X Cap Sense Low Power Ipd vs. Vdd

    260
  • FIGURE 24-41: PIC16F72X T1OSC 32 Khz Ipd vs. Vdd, Vcap = 0.1µF

    261
  • FIGURE 24-42: PIC16LF72X T1OSC 32 Khz Ipd vs. Vdd

    261
  • FIGURE 24-43: PIC16F72X TYpical ADC Ipd vs. Vdd, Vcap = 0.1µF

    262
  • FIGURE 24-44: PIC16LF72X Typical ADC Ipd vs. Vdd

    262
  • FIGURE 24-45: PIC16F72X ADC Ipd vs. Vdd, Vcap = 0.1µF

    263
  • FIGURE 24-46: PIC16LF72X ADC Ipd vs. Vdd

    263
  • FIGURE 24-47: PIC16F72X WDT Ipd vs. Vdd, Vcap = 0.1µF

    264
  • FIGURE 24-48: PIC16LF72X WDT Ipd vs. Vdd

    264
  • FIGURE 24-49: TTL Input Threshold Vin vs. Vdd over Temperature

    265
  • FIGURE 24-50: SCHMITT TRIGGER Input Threshold Vin vs. Vdd Over Temperature

    265
  • FIGURE 24-51: SCHMITT TRIGGER Input Threshold Vin vs. Vdd Over Temperature

    266
  • FIGURE 24-52: Voh vs. Ioh Over Temperature, Vdd = 5.5V

    266
  • FIGURE 24-53: Voh vs. Ioh Over Temperature, Vdd = 3.6V

    267
  • FIGURE 24-54: Voh vs. Ioh Over Temperature, Vdd = 1.8V

    267
  • FIGURE 24-55: Vol vs. Iol Over Temperature, Vdd = 5.5V

    268
  • FIGURE 24-56: Vol vs. Iol Over Temperature, Vdd = 3.6

    268
  • FIGURE 24-57: Vol vs. Iol over Temperature, Vdd = 1.8V

    269
  • FIGURE 24-58: PIC16F72X PWRT Period

    269
  • FIGURE 24-59: PIC16F72X WDT Time-out Period

    270
  • FIGURE 24-60: PIC16F72X HFINTOSC Wake-up from Sleep Start-up Time

    270
  • FIGURE 24-61: PIC16F72X A/D Internal RC Oscillator Period

    271
  • FIGURE 24-62: PIC16F72X Cap Sense Output Current, Power Mode = High

    271
  • FIGURE 24-63: PIC16F72X Cap Sense Output Current, Power Mode = Medium

    272
  • FIGURE 24-64: PIC16F72X Cap Sense Output Current, Power Mode = Low

    272
  • FIGURE 24-65: PIC16F72X Cap sensor Hysteresis, Power Mode = High

    273
  • FIGURE 24-66: PIC16F72X Cap sensor Hysteresis, power Mode = Medium

    273
  • FIGURE 24-67: PIC16F72X Cap sensor Hysteresis, power Mode = LOw

    274
  • FIGURE 24-68: Typical FVR (x1 and x2) vs. Supply Voltage (V) Normalized at 3.0V

    274
  • FIGURE 24-69: Typical FVR Change vs. Temperature Normalized at 25°C

    275
• 25.0 Packaging Information

  277
  • 25.1 Package Marking Information

    277
  • Package Marking Information (Continued)

    278
  • 25.2 Package Details

    279
• Appendix A: Data Sheet Revision History

  291
  • Revision A

    291
  • Revision B

    291
  • Revision C

    291
  • Revision D

    291
  • Revision E

    291
• Appendix B: Migrating From Other PIC® Devices

  291
  • TABLE B-1: Feature Comparison

    291
• INDEX

  293
• The Microchip Web Site

  299
• Customer Change Notification Service

  299
• Customer Support

  299
• Reader Response

  300
• Product Identification System

  301
• Worldwide Sales

  302