Hoja De DatosTabla de contenidosTABLE 1: Silicon DEVREV Values1TABLE 2: Silicon Issue Summary2Silicon Errata Issues31. Module: MSSP (I2C™ Slave)32. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)33. Module: Real-Time Clock and Calendar (RTCC)34. Module: Real-Time Clock and Calendar (RTCC)45. Module: MSSP (I2C™ Mode)4Data Sheet Clarifications51. Module: Guidelines for Getting Started with PIC18FJ Microcontrollers52.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)5FIGURE 2-3 Frequency vs. ESR Performance for Suggested Vcap5TABLE 2-1 Suitable Capacitor Equivalents5FIGURE 2-4 DC Bias Voltage vs. Capacitance Characteristics62. Module: Vbor Specification729.1 DC Characteristics: Supply Voltage PIC18F86J72/87J72 (Industrial)7Appendix A: Document Revision History8Worldwide Sales and Service10Tamaño: 100 KBPáginas: 10Language: EnglishManuales abiertas
Hoja De DatosTabla de contenidosTrademarks21.1 Introduction92.1 Introduction112.2 Types of Calibration112.2.1 Calibration Requirements122.3 Closed Loop Calibration122.3.1 Generic Flow chart for closed Loop calibration132.3.2 ENERGY CALIBRATION142.3.2.1 Active Energy Signal flow and Calibration142.3.2.2 Active energy Gain Computation152.3.2.3 PHASE COMPENSATION152.3.2.4 Active Energy Calibration Procedure182.3.3 Reactive Energy Signal Flow and Calibration202.3.3.1 Reactive Energy Gain Computation202.3.3.2 Reactive Energy Calibration Procedure212.3.4 Power Calibration222.3.4.1 Voltage signal flow and Calibration222.3.4.2 Current signal flow and Calibration232.3.4.3 Active Power signal flow and Calibration252.3.4.4 Reactive Power signal flow and Calibration282.4 Multipoint Calibration302.4.1 IB, VB, Meter Constant and Calibration Configurations30Example 2-1:302.4.2 Active Power and Energy Signal Flow and Calibration31Table 2-1: Calibration Registers Generated through this Routine322.4.3 RMS Current, RMS Voltage, Signal Flow and Calibration33Table 2-2: RMS Current, rms voltage, calibration registers332.4.4 Flow Chart for C1 Configuration – Active Energy, Active Power Gain342.4.4.1 Equations for Configuration C1 Calibration – Active Energy and Active Power352.4.5 Reactive Power and Energy Signal Flow and Calibration36Table 2-3: Calibration Registers Generated through this Routine362.4.6 Configuration C2 Flow Chart – Reactive Power and Energy372.4.6.1 Equations for Configuration C2 Calibration – Reactive Energy and Reactive Power382.4.7 Configuration C2 Flow Chart – Phase Delay,392.4.7.1 Equations for Configuration C2 Calibration – Phase Delay402.4.8 Configuration C3 Flow Chart – Reactive Power Offset412.4.8.1 Equations for Configuration C3 Calibration – Reactive Power Offset422.4.9 Configuration C4 Flow Chart - Active Power Offset432.4.9.1 Equations for Configuration C4 Calibration – Active Power Offset442.4.10 Flow Chart for RMS Calibration452.4.10.1 Equations for Configuration C5 Calibration – RMS Voltage and Current462.5 Single Point Calibration48Table 2-4: Calibration Registers Generated through this Routine48Table 2-5: Calibration Registers Generated through this Routine482.6 Creep Threshold Calibration492.6.1 Creep Threshold Computation492.6.2 Creep Threshold Calibration procedure492.7 Meter Specifications And Calibration Parameters51Table 2-6: Current Resolution Table51Table 2-7: Power Resolution Table51Table 2-8: Voltage Resolution Table513.1 Introduction533.2 Main Screen53Table 3-1: Registers readings of the meter543.2.1 Decimal Point Location553.3 Debug Mode563.3.1 Monitoring Individual Registers563.3.2 Refreshing Registers Status573.3.3 Writing to Individual Registers574.1 Protocol594.1.1 Command Description594.1.1.1 “E” Echo: - to detect the meter connection594.1.1.2 “L” LOAD: Load calibration registers from flash594.1.1.3 “S” Store: Store calibration registers into flash594.1.1.4 “W” Write: Write Starting At Specified Address60Table 4-1: Write Command Examples604.1.1.5 “R” read: Read starting at specified address60Table 4-2: Read Command Examples60Corporate Office62Atlanta62Boston62Chicago62Cleveland62Fax: 216-447-064362Dallas62Detroit62Indianapolis62Toronto62Fax: 852-2401-343162Australia - Sydney62China - Beijing62China - Shanghai62India - Bangalore62Korea - Daegu62Korea - Seoul62Singapore62Taiwan - Taipei62Fax: 43-7242-2244-39362Denmark - Copenhagen62France - Paris62Germany - Munich62Italy - Milan62Spain - Madrid62UK - Wokingham62Worldwide Sales and Service62Worldwide Sales and Service62Tamaño: 1 MBPáginas: 62Language: EnglishManuales abiertas
Hoja De DatosTabla de contenidosTrademarks21.1 Introduction111.2 What the Energy Monitoring PICtail™ Plus Daughter Board User’s Guide kit Includes121.3 Getting Started121.3.1 Step 1: Wiring connections121.3.2 Step 2: Connect the board to a PC running the energy meter software122.1 Overview132.2 Input and Analog Front End152.3 Power Supply Circuit16Chapter 3. Calculation Engine and Register Description173.1 Calculation Engine Signal Flow Summary173.2 Complete Register List183.3 MODE193.4 STATUS203.5 CAL_CONTROL213.6 LINE_CYC223.7 LINE_CYC_CNT223.8 RAW2_I_RMS223.9 RAW_I_RMS223.10 I_RMS223.11 RAW2_V_RMS233.12 RAW_V_RMS233.13 V_RMS233.14 LINE_FREQUENCY233.15 RAW_POWER_ACT243.16 POWER_ACT243.17 POWER_APP243.18 RAW_POWER_REACT243.19 POWER_REACT253.20 PERIOD253.21 ENERGY_ACT253.22 ENERGY_APP253.23 I_ABS_MAX263.24 V_ABS_MAX263.25 ENERGY_REACT263.26 PHASE_COMPENSATION263.27 OFFSET_I_RMS263.28 OFFSET_V_RMS273.29 GAIN_I_RMS273.30 GAIN_V_RMS273.31 OFFSET_POWER_ACT273.32 GAIN_POWER_ACT273.33 OFFSET_POWER_REACT283.34 GAIN_POWER_REACT283.35 GAIN_ENERGY_ACT283.36 GAIN_ENERGY_APP283.37 GAIN_ENERGY_REACT283.38 CF_PULSE_WIDTH293.39 GAIN_DENR_ENERGY_ACT293.40 GAIN_NUMR_ENERGY_ACT293.41 MODE1_DEF293.42 CAL_STATUS303.43 MAXIMUM CURRENT303.44 CALIBRATION_VOLTAGE303.45 CALIBRATION_CURRENT303.46 CALIBRATION_FREQUENCY313.47 METER_CONSTANT313.48 CALIBRATION_LINE_CYCLE313.49 GAIN_DENR_ENERGY_REACT313.50 GAIN_NUMR_ENERGY_REACT313.51 PHASE_COMPENSATION_90313.52 CREEP_THRSHOLD_MINUTE323.53 CREEP_THRSHOLD_SECOND323.54 ENERGY_ACT_FORWARD323.55 ENERGY_ACT_REVERSE323.56 ENERGY_REACT_INDUCTIVE323.57 ENERGY_REACT_CAPACITIVE33A.1 Introduction35A.2 Schematics and PCB Layout35A.3 Board – Schematic36A.4 Board – Schematic Isolation37A.5 Board – Top Silk38A.6 Board – Top Traces and Pads39A.7 Board – Top Traces and Silk40A.8 Board – Bottom Traces and Pads41A.9 Board – Bottom Silk42Table B-1: Bill of MAterials (BOM)43Corporate Office47Atlanta47Boston47Chicago47Cleveland47Fax: 216-447-064347Dallas47Detroit47Indianapolis47Toronto47Fax: 852-2401-343147Australia - Sydney47China - Beijing47China - Shanghai47India - Bangalore47Korea - Daegu47Korea - Seoul47Singapore47Taiwan - Taipei47Fax: 43-7242-2244-39347Denmark - Copenhagen47France - Paris47Germany - Munich47Italy - Milan47Spain - Madrid47UK - Wokingham47Worldwide Sales and Service47Worldwide Sales and Service47Tamaño: 1000 KBPáginas: 47Language: EnglishManuales abiertas
Hoja De DatosTabla de contenidosAnalog Features:3LCD Driver and Keypad Interface Features:3Flexible Oscillator Structure:3Low-Power Features:3Peripheral Highlights:3Special Microcontroller Features:3Target Applications:3Pin Diagram4Typical Application Circuit: Single-Phase Power Meter5Table of Contents6Most Current Data Sheet7Errata7Customer Notification System71.0 Device Overview91.1 Core Features91.1.1 nanoWatt Technology91.1.2 Oscillator Options and Features91.1.3 Memory Options91.1.4 Extended Instruction Set91.1.5 Easy Migration91.2 Analog Features101.3 LCD Driver101.4 Other Special Features101.5 Details on Individual Family Members11TABLE 1-1: Device Features for the PIC18F8XJ72 (80-pin Devices)11FIGURE 1-1: PIC18F8XJ72 (80-pin) Block Diagram12TABLE 1-2: PIC18F8XJ72 Pinout I/O Descriptions132.0 Guidelines for Getting Started with PIC18FJ Microcontrollers212.1 Basic Connection Requirements21FIGURE 2-1: Recommended Minimum connections212.2 Power Supply Pins222.2.1 Decoupling Capacitors222.2.2 Tank Capacitors222.3 Master Clear (MCLR) Pin22FIGURE 2-2: Example of MCLR Pin Connections222.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)23FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap232.5 ICSP Pins232.6 External Oscillator Pins242.7 Unused I/Os24FIGURE 2-4: Suggested Placement of the Oscillator Circuit243.0 Oscillator Configurations253.1 Oscillator Types25FIGURE 3-1: PIC18F87J72 Family Clock Diagram253.2 Control Registers26Register 3-1: OSCCON: Oscillator Control Register(1)26Register 3-2: OSCTUNE: Oscillator Tuning Register273.3 Clock Sources and Oscillator Switching273.3.1 Clock Source Selection283.3.2 Oscillator Transitions283.4 External Oscillator Modes293.4.1 Crystal Oscillator/Ceramic Resonators (HS Modes)29TABLE 3-1: Capacitor Selection for Ceramic Resonators29TABLE 3-2: Capacitor Selection for Crystal Oscillator29FIGURE 3-2: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)293.4.2 External Clock Input (EC Modes)30FIGURE 3-3: External Clock Input Operation (EC Configuration)30FIGURE 3-4: External Clock Input Operation (HS OSC Configuration)303.4.3 PLL Frequency Multiplier30FIGURE 3-5: PLL Block Diagram303.5 Internal Oscillator Block313.5.1 INTIO Modes31FIGURE 3-6: INTIO1 Oscillator Mode31FIGURE 3-7: INTIO2 Oscillator Mode313.5.2 INTPLL Modes313.5.3 Internal Oscillator Output Frequency and Tuning323.5.4 INTOSC Frequency Drift323.6 Effects of Power-Managed Modes on the Various Clock Sources333.7 Power-up Delays33TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode334.0 Power-Managed Modes354.1 Selecting Power-Managed Modes354.1.1 Clock Sources354.1.2 Entering Power-Managed Modes35TABLE 4-1: Power-Managed Modes354.1.3 Clock Transitions and Status Indicators364.1.4 Multiple Sleep Commands364.2 Run Modes364.2.1 PRI_RUN Mode364.2.2 SEC_RUN Mode36FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode37FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)374.2.3 RC_RUN Mode38FIGURE 4-3: Transition Timing to RC_RUN Mode38FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode384.3 Sleep Mode394.4 Idle Modes39FIGURE 4-5: Transition Timing for Entry to Sleep Mode39FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)394.4.1 PRI_IDLE Mode404.4.2 SEC_IDLE Mode40FIGURE 4-7: Transition Timing for Entry to Idle Mode40FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode404.4.3 RC_IDLE Mode414.5 Exiting Idle and Sleep Modes414.5.1 Exit By Interrupt414.5.2 Exit By WDT Time-out414.5.3 Exit By Reset414.5.4 Exit Without an Oscillator Start-up Delay415.0 Reset435.1 RCON Register43FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit43Register 5-1: RCON: Reset Control Register445.2 Master Clear (MCLR)455.3 Power-on Reset (POR)455.4 Brown-out Reset (BOR)45FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)455.4.1 Detecting BOR455.5 Configuration Mismatch (CM)455.6 Power-up Timer (PWRT)465.6.1 Time-out Sequence46FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)46FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 146FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 247FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)475.7 Reset State of Registers48TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register48TABLE 5-2: Initialization Conditions for All Registers496.0 Memory Organization556.1 Program Memory Organization55FIGURE 6-1: Memory Maps for PIC18F87J72 Family Devices556.1.1 Hard Memory Vectors56FIGURE 6-2: Hard Vector and Configuration Word Locations for PIC18F87J72 Family Family Devices566.1.2 Flash Configuration Words56TABLE 6-1: Flash Configuration Word for PIC18F87J72 Family Devices566.1.3 Program Counter576.1.4 Return Address Stack57FIGURE 6-3: Return Address Stack and Associated Registers57Register 6-1: STKPTR: Stack Pointer Register586.1.5 Fast Register Stack59EXAMPLE 6-1: Fast Register Stack Code Example596.1.6 Look-up Tables in Program Memory59EXAMPLE 6-2: Computed GOTO Using an Offset Value596.2 PIC18 Instruction Cycle606.2.1 Clocking Scheme606.2.2 Instruction Flow/Pipelining60FIGURE 6-4: Clock/ Instruction Cycle60EXAMPLE 6-3: Instruction Pipeline Flow606.2.3 Instructions in Program Memory61FIGURE 6-5: Instructions in Program Memory616.2.4 Two-Word Instructions61EXAMPLE 6-4: Two-Word Instructions616.3 Data Memory Organization626.3.1 Bank Select Register62FIGURE 6-6: Data Memory Map for PIC18F86J72 and PIC18F87J72 Devices63FIGURE 6-7: Use of the Bank Select Register (Direct Addressing)646.3.2 Access Bank646.3.3 General Purpose Register File646.3.4 Special Function Registers65TABLE 6-2: Special Function Register Map for PIC18F87J72 Family Devices65TABLE 6-3: PIC18F87J72 Family Register File Summary666.3.5 STATUS Register70Register 6-2: Status Register706.4 Data Addressing Modes716.4.1 Inherent and Literal Addressing716.4.2 Direct Addressing716.4.3 Indirect Addressing71EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing71FIGURE 6-8: Indirect Addressing726.5 Program Memory and the Extended Instruction Set736.6 Data Memory and the Extended Instruction Set746.6.1 Indexed Addressing with Literal Offset746.6.2 Instructions Affected By Indexed Literal Offset Mode74FIGURE 6-9: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)756.6.3 Mapping the Access Bank in Indexed Literal Offset Mode766.6.4 BSR in Indexed Literal Offset Mode76FIGURE 6-10: Remapping the Access Bank with Indexed Literal Offset Addressing767.0 Flash Program Memory777.1 Table Reads and Table Writes77FIGURE 7-1: TABLE READ Operation77FIGURE 7-2: Table Write Operation787.2 Control Registers787.2.1 EECON1 and EECON2 Registers78Register 7-1: EECON1: EEPROM Control Register 1797.2.2 Table Latch Register (TABLAT)807.2.3 Table Pointer Register (TBLPTR)807.2.4 Table Pointer Boundaries80TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions80FIGURE 7-3: Table Pointer Boundaries Based on Operation807.3 Reading the Flash Program Memory81FIGURE 7-4: Reads from Flash Program Memory81EXAMPLE 7-1: Reading a Flash Program Memory Word817.4 Erasing Flash Program Memory827.4.1 Flash Program Memory Erase Sequence82EXAMPLE 7-2: Erasing Flash Program Memory827.5 Writing to Flash Program Memory83FIGURE 7-5: Table Writes to Flash Program Memory837.5.1 Flash Program Memory Write Sequence83EXAMPLE 7-3: Writing to Flash Program Memory847.5.2 FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PROGRAMMING).85EXAMPLE 7-4: SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY857.5.3 Write Verify867.5.4 Unexpected Termination of Write Operation867.6 Flash Program Operation During Code Protection86TABLE 7-2: Registers Associated with Program Flash Memory868.0 8 X 8 Hardware Multiplier878.1 Introduction878.2 Operation87EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine87EXAMPLE 8-2: 8 x 8 Signed Multiply Routine87TABLE 8-1: Performance Comparison for Various Multiply Operations87EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm88EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine88EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm88EXAMPLE 8-4: 16 x 16 Signed Multiply Routine889.0 Interrupts89FIGURE 9-1: PIC18F87J72 Family Interrupt Logic909.1 INTCON Registers91Register 9-1: INTCON: Interrupt Control Register91Register 9-2: INTCON2: Interrupt Control Register 292Register 9-3: INTCON3: Interrupt Control Register 3939.2 PIR Registers94Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 194Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 295Register 9-6: PIR3: Peripheral Interrupt Request (Flag) Register 3969.3 PIE Registers97Register 9-7: PIE1: Peripheral Interrupt Enable Register 197Register 9-8: PIE2: Peripheral Interrupt Enable Register 298Register 9-9: PIE3: Peripheral Interrupt Enable Register 3999.4 IPR Registers100Register 9-10: IPR1: Peripheral Interrupt Priority Register 1100Register 9-11: IPR2: Peripheral Interrupt Priority Register 2101Register 9-12: IPR3: Peripheral Interrupt Priority Register 31029.5 RCON Register103Register 9-13: RCON: Reset Control Register1039.6 INTx Pin Interrupts1049.7 TMR0 Interrupt1049.8 PORTB Interrupt-on-Change1049.9 Context Saving During Interrupts104EXAMPLE 9-1: Saving STATUS, WREG and BSR Registers in RAM10410.0 I/O Ports105FIGURE 10-1: Generic I/O Port Operation10510.1 I/O Port Pin Capabilities10510.1.1 Input Pins and Voltage Considerations105TABLE 10-1: Input Voltage Tolerance10510.1.2 Pin Output Drive105TABLE 10-2: Output Drive Levels for Various ports10610.1.3 Pull-up Configuration10610.1.4 Open-Drain OUTPUTs106FIGURE 10-2: Using the Open-Drain Output (USART Shown as Example)10610.2 PORTA, TRISA and LATA Registers106EXAMPLE 10-1: Initializing PORTA106TABLE 10-3: PORTA Functions107TABLE 10-4: Summary of Registers Associated with PORTA10710.3 PORTB, TRISB and LATB Registers108EXAMPLE 10-2: Initializing PORTB108TABLE 10-5: PORTB Functions109TABLE 10-6: Summary of Registers Associated with PORTB11010.4 PORTC, TRISC and LATC Registers111EXAMPLE 10-3: Initializing PORTC111TABLE 10-7: PORTC Functions112TABLE 10-8: Summary of Registers Associated with PORTC11310.5 PORTD, TRISD and LATD Registers114EXAMPLE 10-4: Initializing PORTD114TABLE 10-9: PORTD Functions115TABLE 10-10: Summary of Registers Associated with PORTD11510.6 PORTE, TRISE and LATE Registers116TABLE 10-11: PORTE Pins Available in Different LCD Drive Configurations116EXAMPLE 10-5: Initializing PORTE116TABLE 10-12: PORTE Functions117TABLE 10-13: Summary of Registers Associated with PORTE11710.7 PORTF, LATF and TRISF Registers118EXAMPLE 10-6: Initializing PORTF118TABLE 10-14: PORTF Functions119TABLE 10-15: Summary of Registers Associated with PORTF12010.8 PORTG, TRISG and LATG Registers121EXAMPLE 10-7: Initializing PORTG121TABLE 10-16: PORTG Functions122TABLE 10-17: Summary of Registers Associated with PORTG12211.0 Timer0 Module123Register 11-1: T0CON: Timer0 Control Register12311.1 Timer0 Operation12411.2 Timer0 Reads and Writes in 16-Bit Mode124FIGURE 11-1: Timer0 Block Diagram (8-Bit Mode)124FIGURE 11-2: Timer0 Block Diagram (16-Bit Mode)12411.3 Prescaler12511.3.1 Switching Prescaler Assignment12511.4 Timer0 Interrupt125TABLE 11-1: Registers Associated with Timer012512.0 Timer1 Module127Register 12-1: T1CON: Timer1 Control Register12712.1 Timer1 Operation128FIGURE 12-1: Timer1 Block Diagram (8-Bit Mode)128FIGURE 12-2: Timer1 Block Diagram (16-Bit Read/Write Mode)12812.2 Timer1 16-Bit Read/Write Mode12912.3 Timer1 Oscillator129FIGURE 12-3: External Components for the Timer1 LP Oscillator129TABLE 12-1: Capacitor Selection for the Timer1 Oscillator(2,3,4)12912.3.1 Using Timer1 as a Clock Source12912.3.2 Timer1 Oscillator Layout Considerations130FIGURE 12-4: Oscillator Circuit with Grounded Guard Ring13012.4 Timer1 Interrupt13012.5 Resetting Timer1 Using the CCP Special Event Trigger13012.6 Using Timer1 as a Real-Time Clock130EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service131TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter13113.0 Timer2 Module13313.1 Timer2 Operation133Register 13-1: T2CON: Timer2 Control Register13313.2 Timer2 Interrupt13413.3 Timer2 Output134FIGURE 13-1: Timer2 Block Diagram134TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter13414.0 Timer3 Module135Register 14-1: T3CON: Timer3 Control Register13514.1 Timer3 Operation136FIGURE 14-1: Timer3 Block Diagram (8-Bit Mode)136FIGURE 14-2: Timer3 Block Diagram (16-Bit Read/Write Mode)13614.2 Timer3 16-Bit Read/Write Mode13714.3 Using the Timer1 Oscillator as the Timer3 Clock Source13714.4 Timer3 Interrupt13714.5 Resetting Timer3 Using the CCP Special Event Trigger137TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter13715.0 Real-Time Clock and Calendar (RTCC)139FIGURE 15-1: RTCC Block Diagram13915.1 RTCC Module Registers140RTCC Control Registers140RTCC Value Registers140Alarm Value Registers14015.1.1 RTCC Control Registers141Register 15-1: RTCCFG: RTCC Configuration Register(1)141Register 15-2: RTCCAL: RTCC Calibration Register142Register 15-3: PADCFG1: Pad Configuration Register142Register 15-4: ALRMCFG: Alarm Configuration Register143Register 15-5: ALRMRPT: Alarm Calibration Register14415.1.2 RTCVALH and RTCVALL Register Mappings144Register 15-6: Reserved Register144Register 15-7: Year: Year Value Register(1)144Register 15-8: MontH: Month Value Register(1)145Register 15-9: Day: Day Value Register(1)145Register 15-10: Weekday: Weekday Value Register(1)145Register 15-11: Hour: Hour Value Register(1)146Register 15-12: MINUTE: Minute Value Register146Register 15-13: SECOND: Second Value Register14615.1.3 ALRMVALH and ALRMVALL Register Mappings147Register 15-14: ALRMMNTH: Alarm Month Value Register(1)147Register 15-15: ALRMDAY: Alarm Day Value Register(1)147Register 15-16: ALRMWd: Alarm Weekday Value Register(1)147Register 15-17: ALRMHr: Alarm Hours Value Register(1)148Register 15-18: ALRMMIN: Alarm Minutes Value Register148Register 15-19: ALRMSEC: Alarm Seconds Value Register14815.1.4 RTCEN Bit Write14915.2 Operation14915.2.1 Register Interface149FIGURE 15-2: Timer Digit Format149FIGURE 15-3: Alarm Digit Format14915.2.2 Clock Source150FIGURE 15-4: Clock Source Multiplexing15015.2.3 Digit Carry Rules150TABLE 15-1: Day of Week Schedule150TABLE 15-2: Day to Month Rollover Schedule15015.2.4 Leap Year15115.2.5 General Functionality15115.2.6 Safety Window for Register Reads and Writes15115.2.7 Write Lock151EXAMPLE 15-1: Setting the RTCWREN Bit15115.2.8 Register Mapping151TABLE 15-3: RTCVALH and RTCVALL Register Mapping151TABLE 15-4: ALRMVAL Register Mapping15215.2.9 Calibration152EQUATION 15-1: Converting Error Clock Pulses15215.3 Alarm15215.3.1 Configuring the Alarm152FIGURE 15-5: Alarm Mask Settings15315.3.2 Alarm Interrupt154FIGURE 15-6: Timer Pulse Generation15415.4 Sleep Mode15415.5 Reset15415.5.1 Device Reset15415.5.2 Power-on Reset (POR)15415.6 Register Maps155TABLE 15-5: RTCC Control Registers155TABLE 15-6: RTCC Value Registers155TABLE 15-7: Alarm Value Registers15516.0 Capture/Compare/PWM (CCP) Modules157Register 16-1: CCPxCON: CCPx Control Register (CCP1, CCP2 Modules)15716.1 CCP Module Configuration15816.1.1 CCP Modules and Timer Resources158TABLE 16-1: CCP Mode – Timer Resource15816.1.2 Open-Drain Output Option15816.1.3 CCP2 Pin Assignment158FIGURE 16-1: CCP and Timer Interconnect Configurations158TABLE 16-2: Interactions Between CCP1 and CCP2 for Timer Resources15916.2 Capture Mode16016.2.1 CCP Pin Configuration16016.2.2 Timer1/Timer3 Mode Selection16016.2.3 Software Interrupt16016.2.4 CCP Prescaler160EXAMPLE 16-1: Changing Between Capture Prescalers160FIGURE 16-2: Capture Mode Operation Block Diagram16016.3 Compare Mode16116.3.1 CCP Pin Configuration16116.3.2 Timer1/Timer3 Mode Selection16116.3.3 Software Interrupt Mode16116.3.4 Special Event Trigger161FIGURE 16-3: Compare Mode Operation Block Diagram161TABLE 16-3: Registers Associated with Capture, Compare, Timer1 and Timer316216.4 PWM Mode163FIGURE 16-4: Simplified PWM Block Diagram163FIGURE 16-5: PWM Output16316.4.1 PWM Period163EQUATION 16-1:16316.4.2 PWM Duty Cycle164EQUATION 16-2:164EQUATION 16-3:164TABLE 16-4: Example PWM Frequencies and Resolutions at 40 MHz16416.4.3 Setup for PWM Operation165TABLE 16-5: Registers Associated with PWM and Timer216517.0 Liquid Crystal Display (LCD) Driver Module167FIGURE 17-1: LCD Driver Module Block Diagram16717.1 LCD Registers16817.1.1 LCD Control Registers168Register 17-1: LCDCON: LCD Control Register168Register 17-2: LCDPS: LCD Phase Register169Register 17-3: LCDSEx: LCD Segment Enable Registers170TABLE 17-1: LCDSE Registers and Associated Segments17017.1.2 LCD Data Registers171Register 17-4: LCDDATAx: LCD Data Registers(1)171TABLE 17-2: LCDDATA Registers and Bits for Segment and COM Combinations17117.2 LCD Clock Source17217.2.1 LCD Voltage Regulator Clock Source17217.2.2 Clock sOURCE cONSIDERATIONS172FIGURE 17-2: LCD Clock Generation17217.3 LCD Bias Generation17317.3.1 LCD Bias Types17317.3.2 LCD Voltage Regulator173Register 17-5: LCDREG: Voltage Regulator Control Register17317.3.3 Bias Configurations174FIGURE 17-3: LCD Regulator connections for M0 and M1 Configurations174FIGURE 17-4: Resistor ladder Connections for M2 configuration175FIGURE 17-5: Resistor ladder Connections for M3 configuration17617.3.4 Design Considerations for The LCD Charge Pump177EQUATION 17-1:17717.4 LCD Multiplex Types177TABLE 17-3: PORTE<6:4> Function17717.5 Segment Enables17717.6 Pixel Control17717.7 LCD Frame Frequency178TABLE 17-4: Frame Frequency Formulas178TABLE 17-5: Approximate Frame Frequency (in Hz) for LP Prescaler Settings17817.8 LCD Waveform Generation178FIGURE 17-6: Type-A/Type-B Waveforms in Static Drive179FIGURE 17-7: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive180FIGURE 17-8: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive181FIGURE 17-9: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive182FIGURE 17-10: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive183FIGURE 17-11: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive184FIGURE 17-12: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive185FIGURE 17-13: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive186FIGURE 17-14: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive187FIGURE 17-15: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive188FIGURE 17-16: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive18917.9 LCD Interrupts190FIGURE 17-17: Example Waveforms and Interrupt Timing in Quarter Duty Cycle Drive19017.10 Operation During Sleep19117.10.1 Using the LCD Regulator During Sleep191FIGURE 17-18: Sleep Entry/Exit When SLPEN = 1 or CS<1:0> = 0019117.11 Configuring the LCD Module192TABLE 17-6: Registers Associated with LCD Operation19318.0 Master Synchronous Serial Port (MSSP) Module19518.1 Master SSP (MSSP) Module Overview19518.2 Control Registers19518.3 SPI Mode195FIGURE 18-1: MSSP Block Diagram (SPI Mode)19518.3.1 Registers196Register 18-1: SSPSTAT: MSSP Status Register (SPI Mode)196Register 18-2: SSPCON1: MSSP Control Register 1 (SPI Mode)19718.3.2 Operation198EXAMPLE 18-1: Loading the SSPBUF (SSPSR) Register19818.3.3 Enabling SPI I/O19918.3.4 Open-Drain Output Option19918.3.5 Typical Connection199FIGURE 18-2: SPI Master/Slave Connection19918.3.6 Master Mode200FIGURE 18-3: SPI Mode Waveform (Master Mode)20018.3.7 Slave Mode20118.3.8 Slave Select Synchronization201FIGURE 18-4: Slave Synchronization Waveform201FIGURE 18-5: SPI Mode Waveform (Slave Mode with CKE = 0)202FIGURE 18-6: SPI Mode Waveform (Slave Mode with CKE = 1)20218.3.9 Operation in Power-Managed Modes20318.3.10 Effects of a Reset20318.3.11 Bus Mode Compatibility203TABLE 18-1: SPI Bus Modes203TABLE 18-2: Registers Associated with SPI Operation20318.4 I2C Mode204FIGURE 18-7: MSSP Block Diagram (I2C™ Mode)20418.4.1 Registers204Register 18-3: SSPSTAT: MSSP Status Register (I2C™ Mode)205Register 18-4: SSPCON1: MSSP Control Register 1 (I2C™ Mode)206Register 18-5: SSPCON2: MSSP Control Register 2 (I2C™ Master Mode)207Register 18-6: SSPCON2: MSSP Control Register 2 (I2C™ Slave Mode)20818.4.2 Operation20918.4.3 Slave Mode209EXAMPLE 18-2: Address Masking Examples210FIGURE 18-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Addressing)212FIGURE 18-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Addressing)213FIGURE 18-10: I2C™ Slave Mode Timing (Transmission, 7-bit Addressing)214FIGURE 18-11: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Addressing)215FIGURE 18-12: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Addressing)216FIGURE 18-13: I2C™ Slave Mode Timing (Transmission, 10-bit Addressing)21718.4.4 Clock Stretching218FIGURE 18-14: Clock Synchronization Timing219FIGURE 18-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Addressing)220FIGURE 18-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Addressing)22118.4.5 General Call Address Support222FIGURE 18-17: Slave Mode General Call Address Sequence (7 or 10-bit Addressing Mode)22218.4.6 Master Mode223FIGURE 18-18: MSSP Block Diagram (I2C™ Master Mode)22318.4.7 Baud Rate225FIGURE 18-19: Baud Rate Generator Block Diagram225TABLE 18-3: I2C™ Clock Rate w/BRG225FIGURE 18-20: Baud Rate Generator Timing with Clock Arbitration22618.4.8 I2C Master Mode Start Condition Timing227FIGURE 18-21: First Start Bit Timing22718.4.9 I2C Master Mode Repeated Start Condition Timing228FIGURE 18-22: Repeated Start Condition Waveform22818.4.10 I2C Master Mode Transmission22918.4.11 I2C Master Mode Reception229FIGURE 18-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Addressing)230FIGURE 18-24: I2C™ Master Mode Waveform (Reception, 7-bit Addressing)23118.4.12 Acknowledge Sequence Timing23218.4.13 Stop Condition Timing232FIGURE 18-25: Acknowledge Sequence Waveform232FIGURE 18-26: Stop Condition Receive or Transmit Mode23218.4.14 Sleep Operation23318.4.15 Effects of a Reset23318.4.16 Multi-Master Mode23318.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration233FIGURE 18-27: Bus Collision Timing for Transmit and Acknowledge233FIGURE 18-28: Bus Collision During Start Condition (SDA Only)234FIGURE 18-29: Bus Collision During Start Condition (SCL = 0)235FIGURE 18-30: BRG Reset Due to SDA Arbitration During Start Condition235FIGURE 18-31: Bus Collision During a Repeated Start Condition (Case 1)236FIGURE 18-32: Bus Collision During Repeated Start Condition (Case 2)236FIGURE 18-33: Bus Collision During a Stop Condition (Case 1)237FIGURE 18-34: Bus Collision During a Stop Condition (Case 2)237TABLE 18-4: Registers Associated with I2C™ Operation23819.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)23919.1 Control Registers239Register 19-1: TXSTA1: EUSART Transmit Status and Control Register240Register 19-2: RCSTA1: EUSART Receive Status and Control Register241Register 19-3: BAUDCON1: Baud Rate Control Register 124219.2 EUSART Baud Rate Generator (BRG)24319.2.1 Operation in Power-Managed Modes24319.2.2 Sampling243TABLE 19-1: Baud Rate Formulas243EXAMPLE 19-1: Calculating Baud Rate Error243TABLE 19-2: Registers Associated with the Baud Rate Generator243TABLE 19-3: Baud Rates For Asynchronous Modes24419.2.3 Auto-Baud Rate Detect246TABLE 19-4: BRG Counter Clock Rates246FIGURE 19-1: Automatic Baud Rate Calculation247FIGURE 19-2: BRG Overflow Sequence24719.3 EUSART Asynchronous Mode24819.3.1 EUSART Asynchronous Transmitter248FIGURE 19-3: EUSART Transmit Block Diagram248FIGURE 19-4: Asynchronous Transmission249FIGURE 19-5: Asynchronous Transmission (Back to Back)249TABLE 19-5: Registers Associated with Asynchronous Transmission24919.3.2 EUSART Asynchronous Receiver25019.3.3 Setting Up 9-bit Mode with Address Detect250FIGURE 19-6: EUSART Receive Block Diagram250FIGURE 19-7: Asynchronous Reception251TABLE 19-6: Registers Associated with Asynchronous Reception25119.3.4 Auto-Wake-up On Sync Break Character252FIGURE 19-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation252FIGURE 19-9: Auto-Wake-up Bit (WUE) Timings During Sleep25219.3.5 Break Character Sequence25319.3.6 Receiving A Break Character253FIGURE 19-10: Send Break Character Sequence25319.4 EUSART Synchronous Master Mode25419.4.1 EUSART Synchronous Master Transmission254FIGURE 19-11: Synchronous Transmission254FIGURE 19-12: Synchronous Transmission (Through TXEN)255TABLE 19-7: Registers Associated with Synchronous Master Transmission25519.4.2 EUSART Synchronous Master Reception256FIGURE 19-13: Synchronous Reception (Master Mode, SREN)256TABLE 19-8: Registers Associated with Synchronous Master Reception25619.5 EUSART Synchronous Slave Mode25719.5.1 EUSART Synchronous Slave Transmit257TABLE 19-9: Registers Associated with Synchronous Slave Transmission25719.5.2 EUSART Synchronous Slave Reception258TABLE 19-10: Registers Associated with Synchronous Slave Reception25820.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)25920.1 Control Registers259Register 20-1: TXSTA2: AUSART Transmit Status and Control Register260Register 20-2: RCSTA2: ausart Receive Status and Control Register26120.2 AUSART Baud Rate Generator (BRG)26220.2.1 Operation in Power-Managed Modes26220.2.2 Sampling262TABLE 20-1: Baud Rate Formulas262EXAMPLE 20-1: Calculating Baud Rate Error262TABLE 20-2: Registers Associated with the Baud Rate Generator262TABLE 20-3: Baud Rates for Asynchronous Modes26320.3 AUSART Asynchronous Mode26420.3.1 AUSART Asynchronous Transmitter264FIGURE 20-1: AUSART Transmit Block Diagram264FIGURE 20-2: Asynchronous Transmission265FIGURE 20-3: Asynchronous Transmission (Back to Back)265TABLE 20-4: Registers Associated with Asynchronous Transmission26520.3.2 AUSART Asynchronous Receiver26620.3.3 Setting Up 9-bit Mode with Address Detect266FIGURE 20-4: AUSART Receive Block Diagram266FIGURE 20-5: Asynchronous Reception267TABLE 20-5: Registers Associated with Asynchronous Reception26720.4 AUSART Synchronous Master Mode26820.4.1 AUSART Synchronous Master Transmission268FIGURE 20-6: Synchronous Transmission268FIGURE 20-7: Synchronous Transmission (Through Txen)269TABLE 20-6: Registers Associated with Synchronous Master Transmission26920.4.2 AUSART Synchronous Master Reception270FIGURE 20-8: Synchronous Reception (Master Mode, SREN)270TABLE 20-7: Registers Associated with Synchronous Master Reception27020.5 AUSART Synchronous Slave Mode27120.5.1 AUSART Synchronous Slave Transmit271TABLE 20-8: Registers Associated with Synchronous Slave Transmission27120.5.2 AUSART Synchronous Slave Reception272TABLE 20-9: Registers Associated with Synchronous Slave Reception27221.0 12-Bit Analog-to-Digital Converter (A/D) Module273Register 21-1: ADCON0: A/D Control Register 0273Register 21-2: ADCON1: A/D Control Register 1274Register 21-3: ADCON2: A/D Control Register 2275FIGURE 21-1: A/D Block Diagram(1,2)276FIGURE 21-2: Analog Input Model27721.1 A/D Acquisition Requirements278EQUATION 21-1: Acquisition Time278EQUATION 21-2: A/D Minimum Charging Time278EQUATION 21-3: Calculating the Minimum Required Acquisition Time27821.2 Selecting and Configuring Automatic Acquisition Time27921.3 Selecting the A/D Conversion Clock279TABLE 21-1: Tad vs. Device Operating Frequencies27921.4 Configuring Analog Port Pins27921.5 A/D Conversions28021.6 Use of the CCP2 Trigger280FIGURE 21-1: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)280FIGURE 21-2: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)28021.7 A/D Converter Calibration28121.8 Operation in Power-Managed Modes281TABLE 21-2: Summary of A/D Registers28122.0 Dual-Channel, 24-Bit Analog Front End (AFE)283FIGURE 22-1: Dual-Channel Analog Front End Functional Diagram28322.1 Functional Overview28422.1.1 Delta-Sigma ADC Architecture28422.1.2 Analog Inputs (CHn+/-)28422.1.3 Programmable Gain Amplifiers (PGA)28422.1.4 SINC3 Filter28422.1.5 Phase Delay Block28422.1.6 Internal AFE Clock28422.1.7 Serial Interface28422.2 AFE Register Map285TABLE 22-1: AFE Register map285TABLE 22-2: Register Map Grouping for Continuous read modes28522.3 Serial Interface28622.3.1 Overview28622.3.2 Control Byte286FIGURE 22-2: Control Byte28622.3.3 Reading from the Device28622.3.4 Writing to the Device28622.3.5 Continuous Communication and Looping On Address Sets28622.3.6 Data Ready Pin (DR)28622.4 AFE Connections28722.4.1 Voltage and ground Connections287FIGURE 22-3: Required Connections for AFE Operation28722.4.2 Serial Interface Connections28822.4.3 Other Interface Connections28822.4.4 ANALOG Inputs28822.5 Using the AFE288EXAMPLE 22-1: Overall Structure for Using the AFE289EXAMPLE 22-2: Initializing the MSSP Module290EXAMPLE 22-3: AFE Clock Source and Interrupt Configuration290EXAMPLE 22-4: Writing and Reading AFE Registers through the MSSP291EXAMPLE 22-5: Reading DATA From AFE During Interrupt29223.0 Comparator Module293Register 23-1: CMCON: Comparator Module Control Register29323.1 Comparator Configuration294FIGURE 23-1: Comparator I/O Operating Modes29423.2 Comparator Operation29523.3 Comparator Reference295FIGURE 23-2: Single Comparator29523.3.1 External Reference Signal29523.3.2 Internal Reference Signal29523.4 Comparator Response Time29523.5 Comparator Outputs295FIGURE 23-3: Comparator Output Block Diagram29623.6 Comparator Interrupts29623.7 Comparator Operation During Sleep29623.8 Effects of a Reset29623.9 Analog Input Connection Considerations297FIGURE 23-4: Comparator Analog Input Model297TABLE 23-1: Registers Associated with Comparator Module29724.0 Comparator Voltage Reference Module29924.1 Configuring the Comparator Voltage Reference299Register 24-1: CVRCON: Comparator Voltage Reference Control Register299FIGURE 24-1: Comparator Voltage Reference Block Diagram30024.2 Voltage Reference Accuracy/Error30024.3 Operation During Sleep30024.4 Effects of a Reset30024.5 Connection Considerations300FIGURE 24-2: Comparator Voltage Reference Output Buffer Example301TABLE 24-1: Registers Associated with Comparator Voltage Reference30125.0 Charge Time Measurement Unit (CTMU)303FIGURE 25-1: CTMU Block Diagram30325.1 CTMU Operation30425.1.1 Theory of Operation30425.1.2 Current Source30425.1.3 Edge Selection and Control30425.1.4 Edge Status30425.1.5 Interrupts30525.2 CTMU Module Initialization30525.3 Calibrating the CTMU Module30525.3.1 Current Source Calibration305FIGURE 25-2: CTMU Current Source Calibration Circuit306EXAMPLE 25-1: Setup for CTMU Calibration Routines307EXAMPLE 25-2: Current Calibration Routine30825.3.2 Capacitance Calibration309EXAMPLE 25-3: Capacitance Calibration Routine31025.4 Measuring Capacitance with the CTMU31125.4.1 Absolute Capacitance Measurement31125.4.2 Relative Charge Measurement311EXAMPLE 25-4: Routine for Capacitive Touch Switch31225.5 Measuring Time with the CTMU Module313FIGURE 25-3: Typical Connections and Internal Configuration for Time Measurement31325.6 Creating a Delay with the CTMU Module314FIGURE 25-4: Typical Connections and Internal Configuration for Pulse Delay Generation31425.7 Operation During Sleep/Idle Modes31425.7.1 Sleep Mode and Deep Sleep Modes31425.7.2 Idle Mode31425.8 Effects of a Reset on CTMU31425.9 Registers315Register 25-1: CTMUCONH: CTMU Control High Register315Register 25-2: CTMUCONL: CTMU Control Low Register316Register 25-3: CTMUICON: CTMU current Control Register317TABLE 25-1: Registers Associated with CTMU Module31726.0 Special Features of the CPU31926.1 Configuration Bits31926.1.1 Considerations for Configuring PIC18F87J72 Family Devices319TABLE 26-1: Mapping of the Flash Configuration Words to the Configuration Registers319TABLE 26-2: Configuration Bits and Device IDs320Register 26-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)321Register 26-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)321Register 26-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)322Register 26-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)323Register 26-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)323Register 26-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)324Register 26-7: DEVID1: Device ID Register 1324Register 26-8: DEVID2: Device ID Register 232426.2 Watchdog Timer (WDT)32526.2.1 Control Register325FIGURE 26-1: WDT Block Diagram325Register 26-9: WDTCON: Watchdog Timer Control Register326TABLE 26-3: Summary of Watchdog Timer Registers32626.3 On-Chip Voltage Regulator32726.3.1 VOLTAGE REGULATION AND LOW-VOLTAGE DETECTION327FIGURE 26-2: Connections for the On-chip Regulator32726.3.2 On-Chip Regulator and BOR32826.3.3 Power-up Requirements32826.3.4 OPERATION IN SLEEP MODE32826.4 Two-Speed Start-up328FIGURE 26-3: Timing Transition for Two-Speed Start-up (INTRC to HSPLL)32826.4.1 Special Considerations for Using Two-Speed Start-up32926.5 Fail-Safe Clock Monitor329FIGURE 26-4: FSCM Block Diagram32926.5.1 FSCM and the Watchdog Timer329FIGURE 26-5: FSCM Timing Diagram33026.5.2 Exiting Fail-Safe Operation33026.5.3 FSCM Interrupts in Power-Managed Modes33026.5.4 POR or Wake-up From Sleep33026.6 Program Verification and Code Protection33126.6.1 Configuration Register Protection33126.7 In-Circuit Serial Programming33126.8 In-Circuit Debugger331TABLE 26-4: Debugger Resources33127.0 Instruction Set Summary33327.1 Standard Instruction Set333TABLE 27-1: Opcode Field Descriptions334FIGURE 27-1: General Format for Instructions336TABLE 27-2: PIC18F87J72 Family Instruction Set33727.1.1 Standard Instruction Set34027.2 Extended Instruction Set37627.2.1 Extended Instruction Syntax376TABLE 27-3: Extensions to the PIC18 Instruction Set37627.2.2 Extended Instruction Set37727.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode38127.2.4 Considerations When Enabling the Extended Instruction Set38127.2.5 Special Considerations with Microchip MPLAB® IDE Tools38328.0 Development Support38528.1 MPLAB Integrated Development Environment Software38528.2 MPLAB C Compilers for Various Device Families38628.3 HI-TECH C for Various Device Families38628.4 MPASM Assembler38628.5 MPLINK Object Linker/ MPLIB Object Librarian38628.6 MPLAB Assembler, Linker and Librarian for Various Device Families38628.7 MPLAB SIM Software Simulator38728.8 MPLAB REAL ICE In-Circuit Emulator System38728.9 MPLAB ICD 3 In-Circuit Debugger System38728.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express38728.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express38828.12 MPLAB PM3 Device Programmer38828.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits38829.0 Electrical Characteristics389Absolute Maximum Ratings(†)389FIGURE 29-1: Voltage-frequency Graph, Regulator Enabled (Industrial)(1)390FIGURE 29-2: Voltage-frequency Graph, Regulator Disabled (Industrial)(1,2)39029.1 DC Characteristics: Supply Voltage PIC18F87J72 Family (Industrial)39129.2 DC Characteristics: Power-Down and Supply Current PIC18F87J72 Family (Industrial)39229.3 DC Characteristics: PIC18F87J72 Family (Industrial)40029.4 DC Characteristics: CTMU Current Source Specifications401TABLE 29-1: Memory Programming Requirements402TABLE 29-2: Comparator Specifications403TABLE 29-3: Voltage Reference Specifications403TABLE 29-4: Internal Voltage Regulator Specifications403TABLE 29-5: Internal LCD Voltage Regulator Specifications40329.5 AC (Timing) Characteristics40429.5.1 Timing Parameter Symbology40429.5.2 Timing Conditions405TABLE 29-6: Temperature and Voltage Specifications – AC405FIGURE 29-3: Load Conditions for Device Timing Specifications40529.5.3 Timing Diagrams and Specifications406FIGURE 29-4: External Clock Timing406TABLE 29-7: External Clock Timing Requirements406TABLE 29-8: PLL Clock Timing Specifications (Vdd = 2.15V to 3.6V)407TABLE 29-9: Internal RC Accuracy (INTOSC and INTRC Sources)407FIGURE 29-5: CLKO and I/O Timing408TABLE 29-10: CLKO and I/O Timing Requirements408FIGURE 29-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing409TABLE 29-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements409FIGURE 29-7: Timer0 and Timer1 External Clock Timings410TABLE 29-12: Timer0 and Timer1 External Clock Requirements410FIGURE 29-8: Capture/Compare/PWM Timings (CCP1, CCP2 Modules)411TABLE 29-13: Capture/Compare/PWM Requirements (CCP1, CCP2 Modules)411FIGURE 29-9: Example SPI Master Mode Timing (CKE = 0)412TABLE 29-14: Example SPI Mode Requirements (Master Mode, Cke = 0)412FIGURE 29-10: Example SPI Master Mode Timing (CKE = 1)413TABLE 29-15: Example SPI Mode Requirements (Master Mode, CKE = 1)413FIGURE 29-11: Example SPI Slave Mode Timing (CKE = 0)414TABLE 29-16: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)414FIGURE 29-12: Example SPI Slave Mode Timing (CKE = 1)415TABLE 29-17: Example SPI Slave Mode Requirements (CKE = 1)415FIGURE 29-13: I2C™ Bus Start/Stop Bits Timing416TABLE 29-18: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)416FIGURE 29-14: I2C™ Bus Data Timing417TABLE 29-19: I2C™ Bus Data Requirements (Slave Mode)417FIGURE 29-15: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms418TABLE 29-20: MSSP I2C™ Bus Start/Stop Bits Requirements418FIGURE 29-16: MSSP I2C™ Bus Data Timing418TABLE 29-21: MSSP I2C™ Bus Data Requirements419FIGURE 29-17: EUSART/AUSART Synchronous Transmission (Master/Slave) Timing420TABLE 29-22: EUSART/AUSART Synchronous Transmission Requirements420FIGURE 29-18: EUSART/AUSART Synchronous Receive (Master/Slave) Timing420TABLE 29-23: EUSART/AUSART Synchronous Receive Requirements420TABLE 29-24: A/D Converter Characteristics: PIC18F87J72 Family (Industrial)421FIGURE 29-19: A/D Conversion Timing422TABLE 29-25: A/D Conversion Requirements422TABLE 29-26: Dual-Channel AFE Electrical Characteristics423TABLE 29-27: Dual-Channel AFE Serial Peripheral Interface Specifications426FIGURE 29-20: Serial Output Timing Diagram427FIGURE 29-21: Serial Input Timing Diagram427FIGURE 29-22: Data Ready Pulse Timing Diagram427FIGURE 29-23: Specific Timing Diagrams42830.0 Packaging Information42930.1 Package Marking Information42930.2 Package Details430Appendix A: Revision History433Revision A (June 2010)433Appendix B: Dual-Channel, 24-Bit AFE Reference434TABLE B-1: OVERSAMPLING RATIO SETTINGS438TABLE B-2: Device data rates in function of mclk, osr AND PRESCALE439TABLE B-3: OVERSAMPLING RATIO SETTINGS439Step 1441Step 2441TABLE B-4: PGA Configuration Setting443TABLE B-5: adc RESOLUTION vs. osr444TABLE B-6: OSR = 256 output code examples446TABLE B-7: OSR = 128 output code examples446TABLE B-8: OSR = 64 output code examples446TABLE B-9: OSR = 32 output code examples446TABLE B-10: Phase Values With MCLK = 4 MHz, OSR = 256448TABLE B-11: Register Groups453TABLE B-12: Register Types453TABLE B-13: Register map456TABLE B-14: Register Map Grouping for Continuous read modes456TABLE B-15: Phase Encoding Resolution By Oversampling Ratio458INDEX465The Microchip Web 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