Hoja De DatosTabla de contenidos1.0 Electrical Characteristics31.1 SPI Mode Timing Waveforms and Requirements12FIGURE 1-1: RESET Waveforms.12TABLE 1-1: RESET Timing12FIGURE 1-2: SPI Timing Waveform (Mode = 11).13TABLE 1-2: SPI Requirements (Mode = 11)13FIGURE 1-3: SPI Timing Waveform (Mode = 00).14TABLE 1-3: SPI Requirements (Mode = 00)142.0 Typical Performance Curves17FIGURE 2-1: Device Current (IDD) vs. SPI Frequency (fSCK) and Ambient Temperature (VDD = 2.7V and 5.5V).17FIGURE 2-2: Device Current (ISHDN) and VDD. (CS = VDD) vs. Ambient Temperature.17FIGURE 2-3: Write Current (IWRITE) vs. Ambient Temperature and VDD.17FIGURE 2-4: CS Pull-up/Pull-down Resistance (RCS) and Current (ICS) vs. CS Input Voltage (VCS) (VDD = 5.5V).17FIGURE 2-5: CS High Input Entry/Exit Threshold vs. Ambient Temperature and VDD.17FIGURE 2-6: 5 kW Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).18FIGURE 2-7: 5 kW Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).18FIGURE 2-8: 5 kW – Nominal Resistance (W) vs. Ambient Temperature and VDD.18FIGURE 2-9: 5 kW Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).18FIGURE 2-10: 5 kW Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).18FIGURE 2-11: 5 kW – RWB (W) vs. Wiper Setting and Ambient Temperature.18FIGURE 2-12: 5 kW – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 µs/Div).19FIGURE 2-13: 5 kW – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 µs/Div).19FIGURE 2-14: 5 kW – Power-Up Wiper Response Time (20 ms/Div).19FIGURE 2-15: 5 kW – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 µs/Div).19FIGURE 2-16: 5 kW – Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 µs/Div).19FIGURE 2-17: 10 kW Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).20FIGURE 2-18: 10 kW Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).20FIGURE 2-19: 10 kW – Nominal Resistance (W) vs. Ambient Temperature and VDD.20FIGURE 2-20: 10 kW Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).20FIGURE 2-21: 10 kW Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).20FIGURE 2-22: 10 kW – RWB (W) vs. Wiper Setting and Ambient Temperature.20FIGURE 2-23: 10 kW – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 µs/Div).21FIGURE 2-24: 10 kW – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 µs/Div).21FIGURE 2-25: 10 kW – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 µs/Div).21FIGURE 2-26: 10 kW – Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 µs/Div).21FIGURE 2-27: 50 kW Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).22FIGURE 2-28: 50 kW Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).22FIGURE 2-29: 50 kW – Nominal Resistance (W) vs. Ambient Temperature and VDD.22FIGURE 2-30: 50 kW Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).22FIGURE 2-31: 50 kW Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).22FIGURE 2-32: 50 kW – RWB (W) vs. Wiper Setting and Ambient Temperature.22FIGURE 2-33: 50 kW – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 µs/Div).23FIGURE 2-34: 50 kW – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 µs/Div).23FIGURE 2-35: 50 kW – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 µs/Div).23FIGURE 2-36: 50 kW – Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 µs/Div).23FIGURE 2-37: 100 kW Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).24FIGURE 2-38: 100 kW Pot Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).24FIGURE 2-39: 100 kW – Nominal Resistance (W) vs. Ambient Temperature and VDD.24FIGURE 2-40: 100 kW Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).24FIGURE 2-41: 100 kW Rheo Mode – RW (W), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).24FIGURE 2-42: 100 kW – RWB (W) vs. Wiper Setting and Ambient Temperature.24FIGURE 2-43: 100 kW – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 µs/Div).25FIGURE 2-44: 100 kW – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 µs/Div).25FIGURE 2-45: 100 kW – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 µs/Div).25FIGURE 2-46: 100 kW – Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 µs/Div).25FIGURE 2-47: VIH (SDI, SCK, CS, and RESET) vs. VDD and Temperature.26FIGURE 2-48: VIL (SDI, SCK, CS, and RESET) vs. VDD and Temperature.26FIGURE 2-49: IOH (SDO) vs. VDD and Temperature.26FIGURE 2-50: IOL (SDO) vs. VDD and Temperature.26FIGURE 2-51: Nominal EEPROM Write Cycle Time vs. VDD and Temperature.27FIGURE 2-52: POR/BOR Trip point vs. VDD and Temperature.27FIGURE 2-53: SCK Input Frequency vs. Voltage and Temperature.272.1 Test Circuits27FIGURE 2-54: -3 db Gain vs. Frequency Test.273.0 Pin Descriptions29TABLE 3-1: Pinout Description for The MCP434X/436X293.1 Chip Select (CS)303.2 Serial Data In (SDI)303.3 Ground (VSS)303.4 Potentiometer Terminal B303.5 Potentiometer Wiper (W) Terminal303.6 Potentiometer Terminal A303.7 Write Protect (WP)303.8 Reset (RESET)303.9 Serial Data Out (SDO)303.10 Positive Power Supply Input (VDD)303.11 Exposed Pad (EP)304.0 Functional Overview314.1 POR/BOR and RESET Operation31FIGURE 4-1: POR/BOR Signal and RESET Pin Interaction.314.2 Memory Map32TABLE 4-1: Memory Map and the Supported Commands32TABLE 4-2: Default FACTORY SETTINGS Selection335.0 Resistor Network39FIGURE 5-1: Resistor Block Diagram.395.1 Resistor Ladder Module395.2 Wiper40TABLE 5-1: Volatile Wiper Value vs. Wiper Position MAP405.3 WiperLock™ Technology405.4 Shutdown41FIGURE 5-2: Resistor Network Shutdown State (RxHW = ‘0’).416.0 Serial Interface (SPI)43FIGURE 6-1: Typical SPI Interface Block Diagram.436.1 SDI, SDO, SCK, and CS Operation44TABLE 6-1: SCK Frequency446.2 The SPI Modes456.3 SPI Waveforms45FIGURE 6-2: 16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).45FIGURE 6-3: 16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).45FIGURE 6-4: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock Technology) - SPI Waveform with PIC MCU (Mode 1,1).46FIGURE 6-5: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock Technology) - SPI Waveform with PIC MCU (Mode 0,0).467.0 Device Commands477.1 Command Byte47TABLE 7-1: Command Bit Overview47FIGURE 7-1: General SPI Command Formats.47TABLE 7-2: Memory Map and the Supported Commands487.2 Data Byte497.3 Error Condition497.4 Continuous Commands50TABLE 7-3: Commands517.5 Write Data52FIGURE 7-2: Write Command - SDI and SDO States.52FIGURE 7-3: Continuous Write Sequence (Volatile Memory only).537.6 Read Data54FIGURE 7-4: Read Command - SDI and SDO States.54FIGURE 7-5: Continuous Read Sequence.557.7 Increment Wiper56FIGURE 7-6: Increment Command - SDI and SDO States.56TABLE 7-4: Increment operation vs. Volatile Wiper Value56FIGURE 7-7: Continuous Increment Command - SDI and SDO States.577.8 Decrement Wiper58FIGURE 7-8: Decrement Command - SDI and SDO States.58TABLE 7-5: Decrement operation vs. Volatile Wiper Value58FIGURE 7-9: Continuous Decrement Command - SDI and SDO States.597.9 Modify Write Protect or WiperLock Technology (High Voltage)60TABLE 7-6: Address Map to Modify Write Protect and WiperLock Technology608.0 Applications Examples618.1 Split Rail Applications61FIGURE 8-1: Example Split Rail System 1.61FIGURE 8-2: Example Split Rail System 2.61TABLE 8-1: VOH - VIH comparisons618.2 Techniques to Force the CS Pin to VIHH62FIGURE 8-3: Using the TC1240A to Generate the VIHH Voltage.62FIGURE 8-4: MCP4XXX Non-volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage.628.3 Using Shutdown Modes62FIGURE 8-5: Example Application Circuit using Terminal Disconnects.628.4 Design Considerations63FIGURE 8-6: Typical Microcontroller Connections.63FIGURE 8-7: Quad Pinout (TSSOP Package) vs. Dual Pinout.63FIGURE 8-8: Layout to support Quad and Dual Devices.64TABLE 8-2: Package Footprint (1)649.0 Development support659.1 Development Tools659.2 Technical Documentation65TABLE 9-1: Development Tools65TABLE 9-2: Technical Documentation6510.0 Packaging Information6710.1 Package Marking Information67Tamaño: 2 MBPáginas: 80Language: EnglishManuales abiertas
Hoja De DatosTabla de contenidosIntroduction5Document Layout5Conventions Used in this Guide6The Microchip Web Site6Customer Support6Document Revision History6Chapter 1. Product Overview71.1 Introduction71.2 What is the 20-Pin TSSOP and SSOP Evaluation Board?71.3 What the 20-Pin TSSOP and SSOP Evaluation Board Kit Includes7Chapter 2. Installation and Operation92.1 Introduction92.2 Features92.3 Getting Started102.4 20-Pin TSSOP and SSOP Evaluation Board Description16Appendix A. Schematic and Layouts25A.1 Introduction25A.2 Schematics and PCB Layout25A.3 Board Schematic26A.4 Board Layout – Top Layer and Silk-Screen27A.5 Board Layout – Bottom Layer28A.6 Board Layout – Power Plane29A.7 Board Layout – Ground Plane30A.8 Board Layout – Top Components31A.9 Board Layout – Bottom Silk32Appendix B. Bill Of Materials (BOM)33Tamaño: 700 KBPáginas: 34Language: EnglishManuales abiertas
