Manual De UsuarioTabla de contenidos1. Introduction31.1 Comparison to the P89LPC932 device31.2 Pin configuration51.3 Pin description71.4 Special function registers131.5 Memory organization202. Clocks212.1 Enhanced CPU212.2 Clock definitions212.3 Clock output212.4 On-chip RC oscillator option222.5 Watchdog oscillator option222.6 External clock input option222.7 Oscillator Clock (OSCCLK) wake-up delay232.8 CPU Clock (CCLK) modification: DIVM register242.9 Low power select243. Interrupts243.1 Interrupt priority structure253.2 External Interrupt pin glitch suppression254. I/O ports274.1 Port configurations284.2 Quasi-bidirectional output configuration284.3 Open drain output configuration294.4 Input-only configuration304.5 Push-pull output configuration304.6 Port 0 and Analog Comparator functions314.7 Additional port features315. Power monitoring functions325.1 Brownout detection325.2 Power-on detection335.3 Power reduction modes336. Reset366.1 Reset vector387. Timers 0 and 1387.1 Mode 0397.2 Mode 1407.3 Mode 2407.4 Mode 3407.5 Mode 6407.6 Timer overflow toggle output428. Real-time clock system timer438.1 Real-time clock source448.2 Changing RTCS1/RTCS0448.3 Real-time clock interrupt/wake-up448.4 Reset sources affecting the Real-time clock449. Capture/Compare Unit (CCU)469.1 CCU Clock (CCUCLK)479.2 CCU Clock prescaling479.3 Basic timer operation479.4 Output compare499.5 Input capture519.6 PWM operation529.7 Alternating output mode539.8 Synchronized PWM register update549.9 HALT549.10 PLL operation549.11 CCU interrupt structure5510. UART5810.1 Mode 05810.2 Mode 15810.3 Mode 25910.4 Mode 35910.5 SFR space5910.6 Baud Rate generator and selection5910.7 Updating the BRGR1 and BRGR0 SFRs6010.8 Framing error6010.9 Break detect6110.10 More about UART Mode 06210.11 More about UART Mode 16310.12 More about UART Modes 2 and 36410.13 Framing error and RI in Modes 2 and 3 with SM2 = 16410.14 Break detect6510.15 Double buffering6510.16 Double buffering in different modes6510.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)6510.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3)6610.19 Multiprocessor communications6710.20 Automatic address recognition6811. I2C interface6911.1 I2C data register7011.2 I2C slave address register7011.3 I2C control register7111.4 I2C Status register7211.5 I2C SCL duty cycle registers I2SCLH and I2SCLL7211.6 I2C operation modes7312. Serial Peripheral Interface (SPI)8312.1 Configuring the SPI8712.2 Additional considerations for a slave8812.3 Additional considerations for a master8812.4 Mode change on SS8812.5 Write collision8912.6 Data mode8912.7 SPI clock prescaler select9313. Analog comparators9313.1 Comparator configuration9313.2 Internal reference voltage9513.3 Comparator input pins9513.4 Comparator interrupt9513.5 Comparators and power reduction modes9513.6 Comparators configuration example9614. Keypad interrupt (KBI)9715. Watchdog timer (WDT)9815.1 Watchdog function9815.2 Feed sequence9915.3 Watchdog clock source10215.4 Watchdog Timer in Timer mode10315.5 Power-down operation10415.6 Periodic wake-up from power-down without an external oscillator10416. Additional features10416.1 Software reset10516.2 Dual Data Pointers10517. Data EEPROM10517.1 Data EEPROM read10617.2 Data EEPROM write10717.3 Hardware reset10717.4 Multiple writes to the DEEDAT register10717.5 Sequences of writes to DEECON and DEEDAT registers10717.6 Data EEPROM Row Fill10717.7 Data EEPROM Block Fill10818. Flash memory10818.1 General description10818.2 Features10818.3 Flash programming and erase10918.4 Using Flash as data storage: IAP-Lite10918.5 In-circuit programming (ICP)11318.6 ISP and IAP capabilities of the P89LPC932A111318.7 Boot ROM11318.8 Power on reset code execution11418.9 Hardware activation of Boot Loader11418.10 In-system programming (ISP)11518.11 Using the In-system programming (ISP)11518.12 In-application programming (IAP)11818.13 IAP authorization key11818.14 Flash write enable11918.15 Configuration byte protection11918.16 IAP error status12018.17 User configuration bytes12318.18 User security bytes12418.19 Boot Vector register12518.20 Boot status register12519. Instruction set12720. Disclaimers13121. Trademarks13122. Contents132Tamaño: 800 KBPáginas: 133Language: EnglishManuales abiertas