Manual De UsuarioTabla de contenidosCover1Notes regarding these materials2General Precautions in the Handling of MPU/MCU Products3Preface5Contents9Section 1 Overview311.1 Features of the SH7785311.2 Block Diagram431.3 Pin Arrangement Table441.4 Pin Arrangement521.5 Physical Memory Address Map54Section 2 Programming Model552.1 Data Formats552.2 Register Descriptions562.2.1 Privileged Mode and Banks562.2.2 General Registers602.2.3 Floating-Point Registers612.2.4 Control Registers632.2.5 System Registers652.3 Memory-Mapped Registers692.4 Data Formats in Registers702.5 Data Formats in Memory702.6 Processing States712.7 Usage Notes732.7.1 Notes on Self-Modifying Code73Section 3 Instruction Set753.1 Execution Environment753.2 Addressing Modes773.3 Instruction Set82Section 4 Pipelining954.1 Pipelines954.2 Parallel-Executability1064.3 Issue Rates and Execution Cycles109Section 5 Exception Handling1195.1 Summary of Exception Handling1195.2 Register Descriptions1195.2.1 TRAPA Exception Register (TRA)1205.2.2 Exception Event Register (EXPEVT)1215.2.3 Interrupt Event Register (INTEVT)1225.2.4 Non-Support Detection Exception Register (EXPMASK)1235.3 Exception Handling Functions1255.3.1 Exception Handling Flow1255.3.2 Exception Handling Vector Addresses1255.4 Exception Types and Priorities1265.5 Exception Flow1285.5.1 Exception Flow1285.5.2 Exception Source Acceptance1305.5.3 Exception Requests and BL Bit1315.5.4 Return from Exception Handling1315.6 Description of Exceptions1325.6.1 Resets1325.6.2 General Exceptions1345.6.3 Interrupts1505.6.4 Priority Order with Multiple Exceptions1515.7 Usage Notes153Section 6 Floating-Point Unit (FPU)1556.1 Features1556.2 Data Formats1566.2.1 Floating-Point Format1566.2.2 Non-Numbers (NaN)1596.2.3 Denormalized Numbers1606.3 Register Descriptions1616.3.1 Floating-Point Registers1616.3.2 Floating-Point Status/Control Register (FPSCR)1636.3.3 Floating-Point Communication Register (FPUL)1666.4 Rounding1676.5 Floating-Point Exceptions1686.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions1686.5.2 FPU Exception Sources1686.5.3 FPU Exception Handling1696.6 Graphics Support Functions1706.6.1 Geometric Operation Instructions1706.6.2 Pair Single-Precision Data Transfer171Section 7 Memory Management Unit (MMU)1737.1 Overview of MMU1747.1.1 Address Spaces1767.2 Register Descriptions1827.2.1 Page Table Entry High Register (PTEH)1837.2.2 Page Table Entry Low Register (PTEL)1847.2.3 Translation Table Base Register (TTB)1857.2.4 TLB Exception Address Register (TEA)1867.2.5 MMU Control Register (MMUCR)1867.2.6 Page Table Entry Assistance Register (PTEA)1897.2.7 Physical Address Space Control Register (PASCR)1907.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR)1927.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)1947.3.1 Unified TLB (UTLB) Configuration1947.3.2 Instruction TLB (ITLB) Configuration1977.3.3 Address Translation Method1977.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1)2007.4.1 Unified TLB (UTLB) Configuration2007.4.2 Instruction TLB (ITLB) Configuration2037.4.3 Address Translation Method2047.5 MMU Functions2077.5.1 MMU Hardware Management2077.5.2 MMU Software Management2077.5.3 MMU Instruction (LDTLB)2087.5.4 Hardware ITLB Miss Handling2107.5.5 Avoiding Synonym Problems2117.6 MMU Exceptions2127.6.1 Instruction TLB Multiple Hit Exception2127.6.2 Instruction TLB Miss Exception2137.6.3 Instruction TLB Protection Violation Exception2147.6.4 Data TLB Multiple Hit Exception2157.6.5 Data TLB Miss Exception2157.6.6 Data TLB Protection Violation Exception2177.6.7 Initial Page Write Exception2187.7 Memory-Mapped TLB Configuration2207.7.1 ITLB Address Array2217.7.2 ITLB Data Array (TLB Compatible Mode)2227.7.3 ITLB Data Array (TLB Extended Mode)2237.7.4 UTLB Address Array2257.7.5 UTLB Data Array (TLB Compatible Mode)2267.7.6 UTLB Data Array (TLB Extended Mode)2277.8 32-Bit Address Extended Mode2297.8.1 Overview of 32-Bit Address Extended Mode2297.8.2 Transition to 32-Bit Address Extended Mode2307.8.3 Privileged Space Mapping Buffer (PMB) Configuration2307.8.4 PMB Function2327.8.5 Memory-Mapped PMB Configuration2337.8.6 Notes on Using 32-Bit Address Extended Mode2347.9 32-Bit Boot Function2377.9.1 Initial Entries to PMB2377.9.2 Notes on 32-Bit Boot2377.10 Usage Notes2397.10.1 Note on Using LDTLB Instruction239Section 8 Caches2418.1 Features2418.2 Register Descriptions2458.2.1 Cache Control Register (CCR)2468.2.2 Queue Address Control Register 0 (QACR0)2488.2.3 Queue Address Control Register 1 (QACR1)2498.2.4 On-Chip Memory Control Register (RAMCR)2508.3 Operand Cache Operation2528.3.1 Read Operation2528.3.2 Prefetch Operation2538.3.3 Write Operation2548.3.4 Write-Back Buffer2558.3.5 Write-Through Buffer2558.3.6 OC Two-Way Mode2568.4 Instruction Cache Operation2578.4.1 Read Operation2578.4.2 Prefetch Operation2578.4.3 IC Two-Way M2588.4.4 Instruction Cache Way Prediction Operation2588.5 Cache Operation Instruction2598.5.1 Coherency between Cache and External Memory2598.5.2 Prefetch Operation2618.6 Memory-Mapped Cache Configuration2628.6.1 IC Address Array2628.6.2 IC Data Array2648.6.3 OC Address Array2648.6.4 OC Data Array2668.6.5 Memory-Mapped Cache Associative Write Operation2678.7 Store Queues2688.7.1 SQ Configu2688.7.2 Writing to SQ2688.7.3 Transfer to External Memory2698.7.4 Determination of SQ Access Exception2708.7.5 Reading from SQ2708.8 Notes on Using 32-Bit Address Extended Mode271Section 9 On-Chip Memory2739.1 Features2739.2 Register Descriptions2769.2.1 On-Chip Memory Control Register (RAMCR)2779.2.2 OL memory Transfer Source Address Register 0 (LSA0)2789.2.3 OL memory Transfer Source Address Register 1 (LSA1)2809.2.4 OL memory Transfer Destination Address Register 0 (LDA0)2829.2.5 OL memory Transfer Destination Address Register 1 (LDA1)2849.3 Operation2869.3.1 Instruction Fetch Access from the CPU2869.3.2 Operand Access from the CPU and Access from the FPU2869.3.3 Access from the SuperHyway Bus Master Module2879.3.4 OL Memory Block Transfer2879.4 On-Chip Memory Protective Functions2909.5 Usage Notes2919.5.1 Page Conflict2919.5.2 Access Across Different Pages2919.5.3 On-Chip Memory Coherency2919.5.4 Sleep Mode2929.6 Note on Using 32-Bit Address Extended Mode292Section 10 Interrupt Controller (INTC)29310.1 Features29310.1.1 Interrupt Method29610.1.2 Interrupt Sources29710.2 Input/Output Pins30210.3 Register Descriptions30310.3.1 External Interrupt Request Registers30710.3.2 User Mode Interrupt Disable Function32810.3.3 On-chip Module Interrupt Priority Registers33010.3.4 Individual On-Chip Module Interrupt Source Registers (INT2B0 to INT2B7)34410.3.5 GPIO Interrupt Set Register (INT2GPIC)35210.4 Interrupt Sources35410.4.1 NMI Interrupts35410.4.2 IRQ Interrupts35410.4.3 IRL Interrupts35510.4.4 On-Chip Peripheral Module Interrupts35710.4.5 Priority of On-Chip Peripheral Module Interrupts35810.4.6 Interrupt Exception Handling and Priority35910.5 Operation36710.5.1 Interrupt Sequence36710.5.2 Multiple Interrupts36910.5.3 Interrupt Masking by MAI Bit36910.6 Interrupt Response Time37010.7 Usage Notes37310.7.1 Example of Handing Routine of IRL Interrupts and Level Detection IRQ Interrupts when ICR0.LVLMODE = 037310.7.2 Notes on Setting IRQ/IRL[7:0] Pin Function37410.7.3 Clearing IRQ and IRL Interrupt Requests375Section 11 Local Bus State Controller (LBSC)37711.1 Features37711.2 Input/Output Pins38011.3 Overview of Areas38411.3.1 Space Divisions38411.3.2 Memory Bus Width38711.3.3 PCMCIA Support38811.4 Register Descriptions39211.4.1 Memory Address Map Select Register (MMSELR)39411.4.2 Bus Control Register (BCR)39711.4.3 CSn Bus Control Register (CSnBCR)40111.4.4 CSn Wait Control Register (CSnWCR)40711.4.5 CSn PCMCIA Control Register (CSnPCR)41211.5 Operation41711.5.1 Endian/Access Size and Data Alignment41711.5.2 Areas42811.5.3 SRAM interface43311.5.4 Burst ROM Interface44211.5.5 PCMCIA Interface44611.5.6 MPX Interface45711.5.7 Byte Control SRAM Interface47111.5.8 Wait Cycles between Access Cycles47611.5.9 Bus Arbitration47811.5.10 Master Mode48011.5.11 Slave Mode48111.5.12 Cooperation between Master and Slave48111.5.13 Power-Down Mode and Bus Arbitration48111.5.14 Mode Pin Settings and General Input Output Port Settings about Data Bus Width48211.5.15 Pins Multiplexed with Other Modules Functions48211.5.16 Register Settings for Divided-Up DACKn Output482Section 12 DDR2-SDRAM Interface (DBSC2)48712.1 Features48712.2 Input/Output Pins49012.3 Data Alignment49512.4 Register Descriptions50912.4.1 DBSC2 Status Register (DBSTATE)51212.4.2 SDRAM Operation Enable Register (DBEN)51312.4.3 SDRAM Command Control Register (DBCMDCNT)51412.4.4 SDRAM Configuration Setting Register (DBCONF)51612.4.5 SDRAM Timing Register 0 (DBTR0)51812.4.6 SDRAM Timing Register 1 (DBTR1)52212.4.7 SDRAM Timing Register 2 (DBTR2)52512.4.8 SDRAM Refresh Control Register 0 (DBRFCNT0)52912.4.9 SDRAM Refresh Control Register 1 (DBRFCNT1)53012.4.10 SDRAM Refresh Control Register 2 (DBRFCNT2)53212.4.11 SDRAM Refresh Status Register (DBRFSTS)53412.4.12 DDRPAD Frequency Setting Register (DBFREQ)53512.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)53712.4.14 SDRAM Mode Setting Register (DBMRCNT)54012.5 DBSC2 Operation54212.5.1 Supported SDRAM Commands54212.5.2 SDRAM Command Issue54312.5.3 Initialization Sequence54612.5.4 Self-Refresh Operation54712.5.5 Auto-Refresh Operation55012.5.6 Regarding Address Multiplexing55112.5.7 Regarding SDRAM Access and Timing Constraints56012.5.8 Important Information Regarding Use of 8-Bank DDR2-SDRAM Products57412.5.9 Important Information Regarding ODT Control Signal Output to SDRAM57412.5.10 DDR2-SDRAM Power Supply Backup Function57612.5.11 Method for Securing Time Required for Initialization, Self-Refresh Cancellation, etc.57912.5.12 Regarding the Supported Clock Ratio57912.5.13 Regarding MCKE Signal Operation580Section 13 PCI Controller (PCIC)58113.1 Features58113.2 Input/Output Pins58413.3 Register Descriptions58713.3.1 PCIC Enable Control Register (PCIECR)59213.3.2 Configuration Registers59313.3.3 PCI Local Registers62013.4 Operation66013.4.1 Supported PCI Commands66013.4.2 PCIC Initialization66113.4.3 Master Access66213.4.4 Target Access67013.4.5 Host Mode67813.4.6 Normal Mode68113.4.7 Power Management68113.4.8 PCI Local Bus Basic Interface683Section 14 Direct Memory Access Controller (DMAC)69514.1 Features69514.2 Input/Output Pins69714.3 Register Descriptions69814.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11)70514.3.2 DMA Source Address Registers B0 to B3, B6 to B9 (SARB0 to SARB3, SARB6 to SARB9)70614.3.3 DMA Destination Address Registers 0 to 11 (DAR0 to DAR11)70714.3.4 DMA Destination Address Registers B0 to B3, B6 to B9 (DARB0 to DARB3, DARB6 to DARB9)70814.3.5 DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11)70914.3.6 DMA Transfer Count Registers B0 to B3, B6 to B9 (TCRB0 to TCRB3, TCRB6 to TCRB9)71014.3.7 DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11)71114.3.8 DMA Operation Register 0, 1 (DMAOR0 and DMAOR1)71914.3.9 DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5)72314.4 Operation73114.4.1 DMA Transfer Requests73114.4.2 Channel Priority73614.4.3 DMA Transfer Types73914.4.4 DMA Transfer Flow74714.4.5 Repeat Mode Transfer74914.4.6 Reload Mode Transfer75014.4.7 DREQ Pin Sampling Timing75114.5 DMAC Interrupt Sources75914.6 Usage Notes76014.6.1 Stopping Modules and Changing Frequency76014.6.2 Address Error76014.6.3 NMI Interrupt76014.6.4 Burst Mode Transfer76014.6.5 Divided-Up DACK Output76014.6.6 DACK/DREQ Setting761Section 15 Clock Pulse Generator (CPG)76315.1 Features76315.2 Input/Output Pins76615.3 Clock Operating Modes76715.4 Register Descriptions76915.4.1 Frequency Control Register 0 (FRQCR0)77115.4.2 Frequency Control Register 1 (FRQCR1)77215.4.3 Frequency Display Register 1 (FRQMR1)77515.4.4 PLL Control Register (PLLCR)77715.5 Calculating the Frequency77815.6 How to Change the Frequency77915.6.1 Changing the Frequency of Clocks Other than the Bus Clock77915.6.2 Changing the Bus Clock Frequency77915.7 Notes on Designing Board786Section 16 Watchdog Timer and Reset (WDT)78916.1 Features78916.2 Input/Output Pins79116.3 Register Descriptions79216.3.1 Watchdog Timer Stop Time Register (WDTST)79316.3.2 Watchdog Timer Control/Status Register (WDTCSR)79416.3.3 Watchdog Timer Base Stop Time Register (WDTBST)79616.3.4 Watchdog Timer Counter (WDTCNT)79716.3.5 Watchdog Timer Base Counter (WDTBCNT)79816.4 Operation79916.4.1 Reset Request79916.4.2 Using Watchdog Timer Mode80116.4.3 Using Interval Timer Mode80116.4.4 Time until WDT Counters Overflow80216.4.5 Clearing WDT Counters80316.5 Status Pin Change Timing during Reset80416.5.1 Power-On Reset by PRESET Pin80416.5.2 Power-On Reset by Watchdog Timer Overflow80716.5.3 Manual Reset by Watchdog Timer Overflow809Section 17 Power-Down Mode81117.1 Features81117.1.1 Types of Power-Down Modes81117.2 Input/Output Pins81317.3 Register Descriptions81317.3.1 Sleep Control Register (SLPCR)81517.3.2 Standby Control Register 0 (MSTPCR0)81617.3.3 Standby Control Register 1 (MSTPCR1)81917.3.4 Standby Display Register (MSTPMR)82117.4 Sleep Mode82317.4.1 Transition to Sleep Mode82317.4.2 Releasing Sleep Mode82317.5 Deep Sleep Mode82417.5.1 Transition to Deep Sleep Mode82417.5.2 Releasing Deep Sleep Mode82517.6 Module Standby Functions82617.6.1 Transition to Module Standby Mode82617.6.2 Releasing Module Standby Functions82617.7 Timing of the Changes on the STATUS Pins82717.7.1 Reset82717.7.2 Releasing Sleep Mode82717.8 DDR-SDRAM Power Supply Backup827Section 18 Timer Unit (TMU)82918.1 Features82918.2 Input/Output Pins83118.3 Register Descriptions83218.3.1 Timer Start Registers (TSTRn) (n = 0, 1)83418.3.2 Timer Constant Registers (TCORn) (n = 0 to 5)83618.3.3 Timer Counters (TCNTn) (n = 0 to 5)83618.3.4 Timer Control Registers (TCRn) (n = 0 to 5)83718.3.5 Input Capture Register 2 (TCPR2)83918.4 Operation84018.4.1 Counter Operation84018.4.2 Input Capture Function84318.5 Interrupts84418.6 Usage Notes84518.6.1 Register Writes84518.6.2 Reading from TCNT84518.6.3 External Clock Frequency845Section 19 Display Unit (DU)84719.1 Features84719.2 Input/Output Pins85019.3 Register Descriptions85119.3.1 Display Unit System Control Register87119.3.2 Display Mode Register (DSMR)87519.3.3 Display Status Register (DSSR)87919.3.4 Display Unit Status Register Clear Register (DSRCR)88319.3.5 Display Unit Interrupt Enable Register (DIER)88419.3.6 Color Palette Control Register (CPCR)88719.3.7 Display Plane Priority Register (DPPR)88919.3.8 Display Unit Extensional Function Enable Register (DEFR)89219.3.9 Horizontal Display Start Register (HDSR)89419.3.10 Horizontal Display End Register (HDER)89519.3.11 Vertical Display Start Register (VDSR)89619.3.12 Vertical Display End Register (VDER)89719.3.13 Horizontal Cycle Register (HCR)89819.3.14 Horizontal Sync Width Register (HSWR)89919.3.15 Vertical Cycle Register (VCR)90019.3.16 Vertical Sync Point Register (VSPR)90119.3.17 Equal Pulse Width Register (EQWR)90219.3.18 Separation Width Register (SPWR)90319.3.19 CLAMP Signal Start Register (CLAMPSR)90419.3.20 CLAMP Signal Width Register (CLAMPWR)90519.3.21 DE Signal Start Register (DESR)90619.3.22 DE Signal Width Register (DEWR)90719.3.23 Color Palette 1 Transparent Color Register (CP1TR)90819.3.24 Color Palette 2 Transparent Color Register (CP2TR)91119.3.25 Color Palette 3 Transparent Color Register (CP3TR)91419.3.26 Color Palette 4 Transparent Color Register (CP4TR)91719.3.27 Display Off Mode Output Register (DOOR)92019.3.28 Color Detection Register (CDER)92119.3.29 Background Plane Output Register (BPOR)92219.3.30 Raster Interrupt Offset Register (RINTOFSR)92419.3.31 Plane n Mode Register (PnMR) (n = 1 to 6)92519.3.32 Plane n Memory Width Register (PnMWR) (n = 1 to 6)92819.3.33 Plane n Blending Ratio Register (PnALPHAR) (n = 1 to 6)92919.3.34 Plane n Display Size X Register (PnDSXR) (n = 1 to 6)93119.3.35 Plane n Display Size Y Register (PnDSYR) (n = 1 to 6)93219.3.36 Plane n Display Position X Register (PnDPXR) (n = 1 to 6)93319.3.37 Plane n Display Position Y Register (PnDPYR) (n = 1 to 6)93419.3.38 Plane n Display Area Start Address 0 Register (PnDSA0R) (n = 1 to 6)93519.3.39 Plane n Display Area Start Address 1 Register (PnDSA1R) (n = 1 to 6)93619.3.40 Plane n Start Position X Register (PnSPXR) (n = 1 to 6)93719.3.41 Plane n Start Position Y Register (PnSPYR) (n = 1 to 6)93819.3.42 Plane n Wrap Around Start Position Register (PnWASPR) (n = 1 to 6)93919.3.43 Plane n Wrap Around Memory Width Register (PnWAMWR) (n = 1 to 6)94019.3.44 Plane n Blinking Time Register (PnBTR) (n = 1 to 6)94119.3.45 Plane n Transparent Color 1 Register (PnTC1R) (n = 1 to 6)94219.3.46 Plane n Transparent Color 2 Register (PnTC2R) (n = 1 to 6)94319.3.47 Plane n Memory Length Register (PnMLR) (n = 1 to 6)94419.3.48 Color Palette 1 Register 000 to 255 (CP1_000R to CP1_255R)94519.3.49 Color Palette 2 Register 000 to 255 (CP2_000R to CP2_255R)94619.3.50 Color Palette 3 Register 000 to 255 (CP3_000R to CP3_255R)94819.3.51 Color Palette 4 Register 000 to 255 (CP4_000R to CP4_255R)94919.3.52 External Synchronization Control Register (ESCR)95119.3.53 Output Signal Timing Adjustment Register (OTAR)95319.4 Operation96019.4.1 Configuration of Output Screen96019.4.2 Display On/Off96319.4.3 Plane Parameter96419.4.4 Memory Allocation96619.4.5 Input Display Data Format96719.4.6 Output Data Format97019.4.7 Endian Conversion97019.4.8 Color Palettes97219.4.9 Superpositioning of Planes97319.4.10 Display Contention97719.4.11 Blinking97919.4.12 Scroll Display98019.4.13 Wraparound Display98119.4.14 Upper-Left Overflow Display98219.4.15 Double Buffer Control98319.4.16 Sync Mode98419.5 Display Control98619.5.1 Display Timing Generation98619.5.2 CSYNC98919.5.3 Scan Method99119.5.4 Color Detection99519.5.5 Output Signal Timing Adjustment99619.5.6 CLAMP Signal and DE Signal99719.6 Power-Down Sequence99819.6.1 Procedures before Executing the Power-Down Sequence99819.6.2 Resetting the Power-Down Sequence998Section 20 Graphics Data Translation Accelerator (GDTA)99920.1 Features99920.2 GDTA Address Space100320.3 Register Descriptions100420.3.1 GA Mask Register (GACMR)100920.3.2 GA Enable Register (GACER)101020.3.3 GA Interrupt Source Indicating Register (GACISR)101120.3.4 GA Interrupt Source Indication Clear Register (GACICR)101220.3.5 GA Interrupt Enable Register (GACIER)101320.3.6 GA CL Input Data Alignment Register (DRCL_CTL)101420.3.7 GA CL Output Data Alignment Register (DWCL_CTL)101520.3.8 GA MC Input Data Alignment Register (DRMC_CTL)101620.3.9 GA MC Output Data Alignment Register (DWMC_CTL)101720.3.10 GA Buffer RAM 0 Data Alignment Register (DCP_CTL)101820.3.11 GA Buffer RAM 1 Data Alignment Register (DID_CTL)101920.3.12 CL Command FIFO (CLCF)102020.3.13 CL Control Register (CLCR)102120.3.14 CL Status Register (CLSR)102320.3.15 CL Frame Width Setting Register (CLWR)102420.3.16 CL Frame Height Setting Register (CLHR)102520.3.17 CL Input Y Padding Size Setting Register (CLIYPR)102620.3.18 CL Input UV Padding Size Setting Register (CLIUVPR)102720.3.19 CL Output Padding Size Setting Register (CLOPR)102820.3.20 CL Palette Pointer Register (CLPLPR)102920.3.21 MC Command FIFO (MCCF)103020.3.22 MC Status Register (MCSR)103320.3.23 MC Frame Width Setting Register (MCWR)103420.3.24 MC Frame Height Setting Register (MCHR)103520.3.25 MC Y Padding Size Setting Register (MCYPR)103620.3.26 MC UV Padding Size Setting Register (MCUVPR)103720.3.27 MC Output Frame Y Pointer Register (MCOYPR)103820.3.28 MC Output Frame U Pointer Register (MCOUPR)103820.3.29 MC Output Frame V Pointer Register (MCOVPR)103920.3.30 MC Past Frame Y Pointer Register (MCPYPR)103920.3.31 MC Past Frame U Pointer Register (MCPUPR)104020.3.32 MC Past Frame V Pointer Register (MCPVPR)104020.3.33 MC Future Frame Y Pointer Register (MCFYPR)104120.3.34 MC Future Frame U Pointer Register (MCFUPR)104120.3.35 MC Future Frame V Pointer Register (MCFVPR)104220.4 GDTA Operation104320.4.1 Explanation of CL Operation104320.4.2 Explanation of MC Operation104920.5 Interrupt Processing105920.6 Data Alignment105920.7 Usage Notes106120.7.1 Regarding Module Stoppage106120.7.2 Regarding Deep Sleep Modes106120.7.3 Regarding Frequency Changes1062Section 21 Serial Communication Interface with FIFO (SCIF)106321.1 Features106321.2 Input/Output Pins106921.3 Register Descriptions107021.3.1 Receive Shift Register (SCRSR)107621.3.2 Receive FIFO Data Register (SCFRDR)107621.3.3 Transmit Shift Register (SCTSR)107721.3.4 Transmit FIFO Data Register (SCFTDR)107721.3.5 Serial Mode Register (SCSMR)107821.3.6 Serial Control Register (SCSCR)108121.3.7 Serial Status Register n (SCFSR)108521.3.8 Bit Rate Register n (SCBRR)109121.3.9 FIFO Control Register n (SCFCR)109221.3.10 Transmit FIFO Data Count Register n (SCTFDR)109421.3.11 Receive FIFO Data Count Register n (SCRFDR)109521.3.12 Serial Port Register n (SCSPTR)109621.3.13 Line Status Register n (SCLSR)109921.3.14 Serial Error Register n (SCRER)110021.4 Operation110121.4.1 Overview110121.4.2 Operation in Asynchronous Mode110421.4.3 Operation in Clocked Synchronous Mode111521.5 SCIF Interrupt Sources and the DMAC112421.6 Usage Notes1126Section 22 Serial I/O with FIFO (SIOF)112922.1 Features112922.2 Input/Output Pins113122.3 Register Descriptions113222.3.1 Mode Register (SIMDR)113422.3.2 Control Register (SICTR)113622.3.3 Transmit Data Register (SITDR)113822.3.4 Receive Data Register (SIRDR)113922.3.5 Transmit Control Data Register (SITCR)114022.3.6 Receive Control Data Register (SIRCR)114122.3.7 Status Register (SISTR)114222.3.8 Interrupt Enable Register (SIIER)114822.3.9 FIFO Control Register (SIFCTR)115022.3.10 Clock Select Register (SISCR)115222.3.11 Transmit Data Assign Register (SITDAR)115322.3.12 Receive Data Assign Register (SIRDAR)115522.3.13 Control Data Assign Register (SICDAR)115622.4 Operation115822.4.1 Serial Clocks115822.4.2 Serial Timing115922.4.3 Transfer Data Format116122.4.4 Register Allocation of Transfer Data116322.4.5 Control Data Interface116522.4.6 FIFO116722.4.7 Transmit and Receive Procedures116922.4.8 Interrupts117422.4.9 Transmit and Receive Timing1176Section 23 Serial Peripheral Interface (HSPI)118123.1 Features118123.2 Input/Output Pins118323.3 Register Descriptions118323.3.1 Control Register (SPCR)118523.3.2 Status Register (SPSR)118823.3.3 System Control Register (SPSCR)119123.3.4 Transmit Buffer Register (SPTBR)119323.3.5 Receive Buffer Register (SPRBR)119423.4 Operation119523.4.1 Operation Overview with FIFO Mode Disabled119523.4.2 Operation with FIFO Mode Enabled119623.4.3 Timing Diagrams119723.4.4 HSPI Software Reset119923.4.5 Clock Polarity and Transmit Control119923.4.6 Transmit and Receive Routines119923.4.7 Flags and Interrupt Timing120023.4.8 Low-Power Consumption and Clock Synchronization1200Section 24 Multimedia Card Interface (MMCIF)120124.1 Features120124.2 Input/Output Pins120224.3 Register Descriptions120324.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5)120724.3.2 Command Start Register (CMDSTRT)120824.3.3 Operation Control Register (OPCR)120924.3.4 Card Status Register (CSTR)121124.3.5 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2)121324.3.6 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2)121724.3.7 Transfer Clock Control Register (CLKON)122324.3.8 Command Timeout Control Register (CTOCR)122424.3.9 Transfer Byte Number Count Register (TBCR)122524.3.10 Mode Register (MODER)122624.3.11 Command Type Register (CMDTYR)122724.3.12 Response Type Register (RSPTYR)122824.3.13 Transfer Block Number Counter (TBNCR)123224.3.14 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD)123324.3.15 Data Timeout Register (DTOUTR)123524.3.16 Data Register (DR)123624.3.17 FIFO Pointer Clear Register (FIFOCLR)123724.3.18 DMA Control Register (DMACR)123824.4 Operation123924.4.1 Operations in MMC Mode123924.5 MMCIF Interrupt Sources126924.6 Operations when Using DMA127024.6.1 Operation in Read Sequence127024.6.2 Operation in Write Sequence128024.7 Register Accesses with Little Endian Specification1291Section 25 Audio Codec Interface (HAC)129325.1 Features129325.2 Input/Output Pins129525.3 Register Descriptions129625.3.1 Control and Status Register (HACCR)129925.3.2 Command/Status Address Register (HACCSAR)130125.3.3 Command/Status Data Register (HACCSDR)130325.3.4 PCM Left Channel Register (HACPCML)130525.3.5 PCM Right Channel Register (HACPCMR)130725.3.6 TX Interrupt Enable Register (HACTIER)130825.3.7 TX Status Register (HACTSR)130925.3.8 RX Interrupt Enable Register (HACRIER)131125.3.9 RX Status Register (HACRSR)131225.3.10 HAC Control Register (HACACR)131425.4 AC 97 Frame Slot Structure131625.5 Operation131825.5.1 Receiver131825.5.2 Transmitter131825.5.3 DMA131925.5.4 Interrupts131925.5.5 Initialization Sequence132025.5.6 Power-Down Mode132525.5.7 Notes132525.5.8 Reference1325Section 26 Serial Sound Interface (SSI) Module132726.1 Features132726.2 Input/Output Pins132926.3 Register Descriptions133026.3.1 Control Register (SSICR)133126.3.2 Status Register (SSISR)133826.3.3 Transmit Data Register (SSITDR)134326.3.4 Receive Data Register (SSIRDR)134326.4 Operation134426.4.1 Bus Format134426.4.2 Non-Compressed Modes134526.4.3 Compressed Modes135426.4.4 Operation Modes135726.4.5 Transmit Operation135826.4.6 Receive Operation136126.4.7 Serial Clock Control136426.5 Usage Note136526.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation136526.5.2 Pin Function Setting for the SSI Module136526.5.3 Usage Note in Slave Mode1365Section 27 NAND Flash Memory Controller (FLCTL)136727.1 Features136727.2 Input/Output Pins137027.3 Register Descriptions137227.3.1 Common Control Register (FLCMNCR)137427.3.2 Command Control Register (FLCMDCR)137627.3.3 Command Code Register (FLCMCDR)137827.3.4 Address Register (FLADR)137927.3.5 Address Register 2 (FLADR2)138127.3.6 Data Counter Register (FLDTCNTR)138227.3.7 Data Register (FLDATAR)138327.3.8 Interrupt DMA Control Register (FLINTDMACR)138427.3.9 Ready Busy Timeout Setting Register (FLBSYTMR)138927.3.10 Ready Busy Timeout Counter (FLBSYCNT)139027.3.11 Data FIFO Register (FLDTFIFO)139127.3.12 Control Code FIFO Register (FLECFIFO)139227.3.13 Transfer Control Register (FLTRCR)139327.4 Operation139427.4.1 Operating Modes139427.4.2 Command Access Mode139427.4.3 Sector Access Mode139827.4.4 Status Read140127.5 Example of Register Setting140327.6 Interrupt Processing140627.7 DMA Transfer Settings1406Section 28 General Purpose I/O Ports (GPIO)140728.1 Features140728.2 Register Descriptions141228.2.1 Port A Control Register (PACR)141628.2.2 Port B Control Register (PBCR)141928.2.3 Port C Control Register (PCCR)142128.2.4 Port D Control Register (PDCR)142328.2.5 Port E Control Register (PECR)142528.2.6 Port F Control Register (PFCR)142728.2.7 Port G Control Register (PGCR)142928.2.8 Port H Control Register (PHCR)143128.2.9 Port J Control Register (PJCR)143328.2.10 Port K Control Register (PKCR)143528.2.11 Port L Control Register (PLCR)143728.2.12 Port M Control Register (PMCR)143928.2.13 Port N Control Register (PNCR)144028.2.14 Port P Control Register (PPCR)144228.2.15 Port Q Control Register (PQCR)144428.2.16 Port R Control Register (PRCR)144628.2.17 Port A Data Register (PADR)144828.2.18 Port B Data Register (PBDR)144928.2.19 Port C Data Register (PCDR)145028.2.20 Port D Data Register (PDDR)145128.2.21 Port E Data Register (PEDR)145228.2.22 Port F Data Register (PFDR)145328.2.23 Port G Data Register (PGDR)145428.2.24 Port H Data Register (PHDR)145528.2.25 Port J Data Register (PJDR)145628.2.26 Port K Data Register (PKDR)145728.2.27 Port L Data Register (PLDR)145828.2.28 Port M Data Register (PMDR)145928.2.29 Port N Data Register (PNDR)146028.2.30 Port P Data Register (PPDR)146128.2.31 Port Q Data Register (PQDR)146228.2.32 Port R Data Register (PRDR)146328.2.33 Port E Pull-Up Control Register (PEPUPR)146428.2.34 Port H Pull-Up Control Register (PHPUPR)146528.2.35 Port J Pull-Up Control Register (PJPUPR)146628.2.36 Port K Pull-Up Control Register (PKPUPR)146728.2.37 Port L Pull-Up Control Register (PLPUPR)146828.2.38 Port M Pull-Up Control Register (PMPUPR)146928.2.39 Port N Pull-Up Control Register (PNPUPR)147028.2.40 Input-Pin Pull-Up Control Register 1 (PPUPR1)147128.2.41 Input-Pin Pull-Up Control Register 2 (PPUPR2)147128.2.42 Peripheral Module Select Register 1 (P1MSELR)147328.2.43 Peripheral Module Select Register 2 (P2MSELR)147728.3 Usage Example147928.3.1 Port Output Function147928.3.2 Port Input function148028.3.3 Peripheral Module Function1481Section 29 User Break Controller (UBC)148329.1 Features148329.2 Register Descriptions148529.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1)148729.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1)149329.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)149529.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)149629.2.5 Match Data Setting Register 1 (CDR1)149829.2.6 Match Data Mask Setting Register 1 (CDMR1)149929.2.7 Execution Count Break Register 1 (CETR1)150029.2.8 Channel Match Flag Register (CCMFR)150129.2.9 Break Control Register (CBCR)150229.3 Operation Description150329.3.1 Definition of Words Related to Accesses150329.3.2 User Break Operation Sequence150429.3.3 Instruction Fetch Cycle Break150529.3.4 Operand Access Cycle Break150629.3.5 Sequential Break150729.3.6 Program Counter Value to be Saved150929.4 User Break Debugging Support Function151029.5 User Break Examples151129.6 Usage Notes1515Section 30 User Debugging Interface (H-UDI)151730.1 Features151730.2 Input/Output Pins151930.3 Register Description152130.3.1 Instruction Register (SDIR)152230.3.2 Interrupt Source Register (SDINT)152230.3.3 Bypass Register (SDBPR)152330.3.4 Boundary Scan Register (SDBSR)152330.4 Operation153330.4.1 Boundary-Scan TAP Controller (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS)153330.4.2 TAP Control153530.4.3 H-UDI Reset153630.4.4 H-UDI Interrupt153730.5 Usage Notes1537Section 31 Register List153931.1 Register Address List153931.2 States of the Registers in the Individual Operating Modes1563Section 32 Electrical Characteristics159132.1 Absolute Maximum Ratings159132.2 DC Characteristics159232.3 AC Characteristics159732.3.1 Clock and Control Signal Timing159832.3.2 Control Signal Timing160232.3.3 Bus Timing160432.3.4 DBSC2 Signal Timing162232.3.5 INTC Module Signal Timing162732.3.6 PCIC Module Signal Timing162932.3.7 DMAC Module Signal Timing163132.3.8 TMU Module Signal Timing163232.3.9 SCIF Module Signal Timing163332.3.10 H-UDI Module Signal Timing163532.3.11 GPIO Signal Timing163732.3.12 HSPI Module Signal Timing163832.3.13 SIOF Module Signal Timing163932.3.14 MMCIF Module Signal Timing164332.3.15 HAC Interface Module Signal Timing164432.3.16 SSI Interface Module Signal Timing164632.3.17 FLCTL Module Signal Timing164832.3.18 Display Unit Signal Timing165232.4 AC Characteristic Test Conditions1655Appendix1657A. Package Dimensions1657B. Mode Pin Settings1658C. Pin Functions1661C.1 Pin States1661C.2 Handling of Unused Pins1672D. Turning On and Off Power Supply1683D.1 Turning On and Off Between Each Power Supply Series1683D.2 Power-On and Power-Off Sequences for Power Supplies with Different Potentials in DDR2-SDRAM Power Supply Backup Mode1684D.3 Turning On and Off Between the Same Power Supply Series1685E. Version Registers (PVR, PRR)1686F. Product Lineup1687Colophon1689Tamaño: 8 MBPáginas: 1692Language: EnglishManuales abiertas