Samsung S3F80JB Manuel D’Utilisation
S3F80JB
LOW VOLTAGE DETECTOR
16-1
16
LOW VOLTAGE DETECTOR
OVERVIEW
The S3F80JB micro-controller has a built-in Low Voltage Detector (LVD) circuit, which allows LVD and
LVD_FLAG detection of power voltage. The S3F80JB has two options in LVD and LVD_FLAG voltage level
according to the operating frequency to be set by smart option (Refer to the page 2-4).
LVD_FLAG detection of power voltage. The S3F80JB has two options in LVD and LVD_FLAG voltage level
according to the operating frequency to be set by smart option (Refer to the page 2-4).
Operating Frequency 4MHz:
•
•
Low voltage detect level for Backup Mode and Reset (LVD): 1.9V (Typ)
± 200mV
•
Low voltage detect level for Flash Flag Bit (LVD_FLAG): 2.15V (Typ)
± 200mV
Operating Frequency 8MHz:
•
Low voltage detect level for Backup Mode and Reset (LVD): 2.15V (Typ)
± 200mV
•
Low voltage detect level for Flash Flag Bit (LVD_FLAG): 2.3V (Typ)
± 200mV
After power-on, LVD block is always enabled. LVD block is only disable when executed STOP instruction with a
smart option setting. The LVD block of S3F80JB consists of two comparators and a resistor string. One of
comparators is for LVD detection, and the other is for LVD_FLAG detection.
smart option setting. The LVD block of S3F80JB consists of two comparators and a resistor string. One of
comparators is for LVD detection, and the other is for LVD_FLAG detection.
LVD
LVD circuit supplies two operating modes by one comparator: back-up mode input and system reset input. The
S3F80JB can enter the back-up mode and generate the reset signal by the LVD level (note1) detection using
LVD circuit. When LVD circuit detects the LVD level (note1) in falling power, S3F80JB enters the Back-up mode.
Back-up mode input automatically creates a chip stop state. When LVD circuit detects the LVD level (note1) in
rising power, the system reset occurs. When the reset pin is at a high state and the LVD circuit detects rising
edge of V
S3F80JB can enter the back-up mode and generate the reset signal by the LVD level (note1) detection using
LVD circuit. When LVD circuit detects the LVD level (note1) in falling power, S3F80JB enters the Back-up mode.
Back-up mode input automatically creates a chip stop state. When LVD circuit detects the LVD level (note1) in
rising power, the system reset occurs. When the reset pin is at a high state and the LVD circuit detects rising
edge of V
DD
on the point V
LVD
, the reset pulse generator makes a reset pulse, and system reset occurs. This
reset by LVD circuit is one of the S3F80JB reset sources. (Refer to the page 8-3 for more.)
LVD FLAG
The other comparator’s output makes LVD indicator flag bit ‘1’ or ‘0’. That is used to indicate low voltage level
(note2). When the power voltage is below the LVD_FLAG level, the bit 0 of LVDCON register is set ‘1’. When the
power voltage is above the LVD_FLAG level, the bit 0 of LVDCON register is set ‘0’ automatically. LVDCON.0
can be used flag bit to indicate low battery in IR application or others.
(note2). When the power voltage is below the LVD_FLAG level, the bit 0 of LVDCON register is set ‘1’. When the
power voltage is above the LVD_FLAG level, the bit 0 of LVDCON register is set ‘0’ automatically. LVDCON.0
can be used flag bit to indicate low battery in IR application or others.