Epson S1D13708 Manuel D’Utilisation
Epson Research and Development
Page 123
Vancouver Design Center
Hardware Functional Specification
S1D13708
Issue Date: 02/03/07
X39A-A-001-02
bits 1-0
PCLK Source Select Bits [1:0]
These bits determine the source of the Pixel Clock (PCLK).
These bits determine the source of the Pixel Clock (PCLK).
Note
Selecting XTAL as the PCLK source is controlled by the BCLK Source Select bit
(REG[C9h] bit 0).
(REG[C9h] bit 0).
8.3.3 Look-Up Table Registers
bits 7-2
LUT Blue Write Data Bits [5:0]
This register contains the data to be written to the blue component of the Look-Up Table.
The data is stored in this register until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
This register contains the data to be written to the blue component of the Look-Up Table.
The data is stored in this register until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written to.
written to.
bits 7-2
LUT Green Write Data Bits [5:0]
This register contains the data to be written to the green component of the Look-Up Table.
The data is stored in this register until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
This register contains the data to be written to the green component of the Look-Up Table.
The data is stored in this register until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written to.
written to.
Table 8-4: PCLK Source Selection
PCLK Source Select Bits 1:0
PCLK Source
00
MCLK
01
BCLK
10
CLKI
11
CLKI2 / XTAL
Look-Up Table Blue Write Data Register
REG[08h]
REG[08h]
Write Only
LUT Blue Write Data Bits 5-0
n/a
7
6
5
4
3
2
1
0
Look-Up Table Green Write Data Register
REG[09h]
REG[09h]
Write Only
LUT Green Write Data Bits 5-0
n/a
7
6
5
4
3
2
1
0