Epson S1D13708 Manuel D’Utilisation
Page 214
Epson Research and Development
Vancouver Design Center
S1D13708
Hardware Functional Specification
X39A-A-001-02
Issue Date: 02/03/07
17.1.2 1/2/4/8 Bpp Color Depth
For 1/2/4/8 bpp color depth, byte swapping must be performed on the bus data but not the
display data.
display data.
For 1/2/4/8 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be
set to 0.
set to 0.
Figure 17-2 Byte-swapping for 1/2/4/8 Bpp
11 22
22
22
11
11
0
15
0
15
D[15:8]
D[7:0]
* High byte lane (D[15:8]) data (e.g. 11) is associated with even address.
* Low byte lane (D[7:0]) data (e.g. 22) is associated with odd address.
* Low byte lane (D[7:0]) data (e.g. 22) is associated with odd address.
CPU Data
Byte Swap
Byte Swap
System
Memory
Memory
Display
Buffer
Buffer
(Big-Endian)
(Little-Endian)
0
0
System
Memory
Address
Memory
Address
Display
Buffer
Address
Buffer
Address