Epson S1D13708 Manuel D’Utilisation
Page 8
Epson Research and Development
Vancouver Design Center
S1D13708
Interfacing to the NEC VR4102 / VR4111 Microprocessors
X39A-G-007-01
Issue Date: 01/11/05
2 Interfacing to the NEC VR4102/VR4111
2.1 The NEC VR41XX System Bus
The VR-Series family of microprocessors features a high-speed synchronous system bus
typical of modern microprocessors. Designed with external LCD controller support and
Windows® CE based embedded consumer applications in mind, the VR4102/VR4111
offers a highly integrated solution for portable systems. This section is an overview of the
operation of the CPU bus to establish interface requirements.
typical of modern microprocessors. Designed with external LCD controller support and
Windows® CE based embedded consumer applications in mind, the VR4102/VR4111
offers a highly integrated solution for portable systems. This section is an overview of the
operation of the CPU bus to establish interface requirements.
2.1.1 Overview
The NEC VR series microprocessor is designed around the RISC architecture developed by
MIPS. The VR4102 microprocessor is designed around the 66MHz VR4100 CPU core and
the VR4111 is designed around the 80/100MHz VR4110 core. These microprocessors
support 64-bit processing. The CPU communicates with the Bus Control Unit (BCU)
through its internal SysAD bus. The BCU in turn communicates with external devices with
its ADD and DATA busses which can be dynamically sized for 16 or 32-bit operation.
MIPS. The VR4102 microprocessor is designed around the 66MHz VR4100 CPU core and
the VR4111 is designed around the 80/100MHz VR4110 core. These microprocessors
support 64-bit processing. The CPU communicates with the Bus Control Unit (BCU)
through its internal SysAD bus. The BCU in turn communicates with external devices with
its ADD and DATA busses which can be dynamically sized for 16 or 32-bit operation.
The NEC VR4102/VR4111 can directly support an external LCD controller through a
dedicated bus interface. Specific control signals are assigned for an external LCD controller
in order to provide an easy interface to the CPU. A 16M byte block of memory is assigned
for the LCD controller with its own chip select and ready signals available. Word or byte
accesses are controlled by the system high byte signal (SHB#).
dedicated bus interface. Specific control signals are assigned for an external LCD controller
in order to provide an easy interface to the CPU. A 16M byte block of memory is assigned
for the LCD controller with its own chip select and ready signals available. Word or byte
accesses are controlled by the system high byte signal (SHB#).