Epson S1D13708 Manuel D’Utilisation
Epson Research and Development
Page 11
Vancouver Design Center
Interfacing to the NEC VR4181A™ Microprocessor
S1D13708
Issue Date: 01/11/05
X39A-G-008-01
3.2 Host Bus Interface Signals
The interface requires the following signals.
• CLKI is a clock input which is required by the S1D13708 Host Bus Interface as a source
for its internal bus and memory clocks. This clock is typically driven by the host CPU
system clock. For this example, SYSCLK from the NEC VR4181A is used for CLKI.
system clock. For this example, SYSCLK from the NEC VR4181A is used for CLKI.
• The address inputs AB[16:0], and the data bus DB[15:0], connect directly to the NEC
VR4181A address (A[16:0]) and data bus (D[15:0]), respectively. CNF4 must be set to
select little endian mode.
select little endian mode.
• Chip Select (CS#) must be driven low by #LCDCS whenever the S1D13708 is accessed
by the VR4181A.
• M/R# (memory/register) selects between memory or register accesses. This signal may
be connected to an address line, allowing system address A17 to be connected to the
M/R# line.
M/R# line.
• WE1# connects to #UBE (the high byte enable signal from the NEC VR4181A) which
in conjunction with address bit 0 allows byte steering of read and write operations.
• WE0# connects to #MEMWR (the write enable signal from the NEC VR4181A) and
must be driven low when the NEC VR4181A is writing data to the S1D13708.
• RD# connects to #MEMRD (the read enable signal from the NEC VR4181A) and must
be driven low when the NEC VR4181A is reading data from the S1D13708.
• WAIT# connects to IORDY and is a signal which is output from the S1D13708 which
indicates the NEC VR4181A must wait until data is ready (read cycle) or accepted
(write cycle) on the host bus. Since VR4181A accesses to the S1D13708 may occur
asynchronously to the display update, it is possible that contention may occur in
accessing the S1D13708 internal registers and/or display buffer. The WAIT# line
resolves these contentions by forcing the host to wait until the resource arbitration is
complete.
(write cycle) on the host bus. Since VR4181A accesses to the S1D13708 may occur
asynchronously to the display update, it is possible that contention may occur in
accessing the S1D13708 internal registers and/or display buffer. The WAIT# line
resolves these contentions by forcing the host to wait until the resource arbitration is
complete.
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in this implemen-
tation of the NEC VR4181A interface using the Generic #2 Host Bus Interface. These
pins must be tied high (connected to IO V
pins must be tied high (connected to IO V
DD
).