Epson S1D13708 Manuel D’Utilisation
Page 42
Epson Research and Development
Vancouver Design Center
S1D13708
Hardware Functional Specification
X39A-A-001-02
Issue Date: 02/03/07
6 A.C. Characteristics
Conditions: CORE
V
DD
= 1.8V ± 10%
IO V
DD
= 3.3V ± 10%
T
A
= TBD
°
C
t
r
and
t
f
for all inputs must be < 5 nsec (10% ~ 90%)
C
L
= 50pF (Bus/MPU Interface)
C
L
= 0pF (LCD Panel Interface)
6.1 Clock Timing
6.1.1 Input Clocks
Figure 6-1 Clock Input Requirements
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page
43 for internal clock requirements.
when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page
43 for internal clock requirements.
Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1
Symbol
Parameter
Min
Max
Units
f
OSC
Input Clock Frequency (CLKI)
100
MHz
T
OSC
Input Clock period (CLKI)
1/f
OSC
ns
t
PWH
Input Clock Pulse Width High (CLKI)
4.5
ns
t
PWL
Input Clock Pulse Width Low (CLKI)
4.5
ns
t
f
Input Clock Fall Time (10% - 90%)
5
ns
t
r
Input Clock Rise Time (10% - 90%)
5
ns
t
PWL
t
PWH
t
f
Clock Input Waveform
tr
T
OSC
V
IH
VIL
10%
90%