Epson S1D13708 Manuel D’Utilisation
Epson Research and Development
Page 45
Vancouver Design Center
Hardware Functional Specification
S1D13708
Issue Date: 02/03/07
X39A-A-001-02
1.
t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-5: Generic #1 Interface Timing
Symbol
Parameter
Min
Max
Unit
f
CLK
Bus Clock frequency
50
MHz
T
CLK
Bus Clock period
1/f
CLK
ns
t3
A[16:0], M/R# setup to first CLK rising edge where CS# = 0 and either RD0#,
RD1# = 0 or WE0#, WE1# = 0
RD1# = 0 or WE0#, WE1# = 0
1
ns
t4
A[16:0], M/R# hold from either RD0#, RD1# or WE0#, WE1# rising edge
0
ns
t5
CS# setup to CLK rising edge
1
ns
t6
CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge
0
ns
t7a
WAIT# asserted for MCLK = BCLK
8
T
CLK
t7b
WAIT# asserted for MCLK = BCLK
÷
2
13
T
CLK
t7c
WAIT# asserted for MCLK = BCLK
÷
3
17
T
CLK
t7d
WAIT# asserted for MCLK = BCLK
÷
4
20
T
CLK
t8
RD0#, RD1#, WE0#, WE1# setup to CLK rising edge
1
ns
t9
Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT# driven low
5
12
ns
t10
Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# high impedance
3
8
ns
t11
D[15:0] setup to third CLK rising edge where CS# = 0 and WE0#, WE1# = 0
(write cycle) (see note 1)
(write cycle) (see note 1)
1
ns
t12
D[15:0] hold from WAIT# rising edge (write cycle)
0
ns
t13
RD0#, RD1# falling edge to D[15:0] driven (read cycle)
4
11
ns
t14
WAIT# rising edge to D[15:0] valid (read cycle)
2
ns
t15
RD0#, RD1# rising edge to D[15:0] high impedance (read cycle)
3
9
ns