Epson S1D13708 Manuel D’Utilisation
Page 10
Epson Research and Development
Vancouver Design Center
S1D13708
Interfacing to the Intel StrongARM SA-1110 Microprocessor
X39A-G-019-01
Issue Date: 01/11/25
Figure 2-2: illustrates a typical variable-latency IO access write cycle on the SA-1110 bus.
Figure 2-2: SA-1110 Variable-Latency IO Write Cycle
A[25:0]
nCS4
nWE
ADDRESS VALID
DATA VALID
D[31:0]
nOE
nCAS[3:0]
RDY