Epson S1D13708 Manuel D’Utilisation

Page 74

Epson Research and Development

Vancouver Design Center

S1D13708

Hardware Functional Specification

X39A-A-001-02

Issue Date: 02/03/07

6.4.3 Single Monochrome 8-Bit Panel Timing

Figure 6-19 Single Monochrome 8-Bit Panel Timing

VDP

= Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines

VNDP

= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines

HDP

= Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts

HNDP

= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)

FPLINE

FPSHIFT

FPFRAME

FPLINE

DRDY (MOD)

* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel

FPDAT[7:0]

FPDAT6

FPDAT5

FPDAT4

FPDAT7

FPDAT2

FPDAT1

FPDAT0

FPDAT3

HNDP

VDP

LINE1

LINE2

LINE3

LINE4

LINE479 LINE480

LINE1

LINE2

1-2

1-10

1-634

1-3

1-11

1-635

1-4

1-12

1-636

1-5

1-13

1-637

1-6

1-14

1-638

1-7

1-15

1-639

1-8

1-16

1-640

1-1

1-9

1-633

VNDP

HDP

Invalid