Renesas rl78 Manuel D’Utilisation
RL78/G1A
CHAPTER 5 CLOCK GENERATOR
R01UH0305EJ0200 Rev.2.00
142
Jul 04, 2013
Figure 5-1. Block Diag
ram
of Clock Generator
System cloc
k control
register (CKC)
Oscillation stabilization
time select register (OSTS)
Oscillation stabilization
time counter status
register (OSTC)
ST
OP mode
signal
Cloc
k oper
ation mode
control register
(CMC)
Cloc
k oper
ation status
control register
(CSC)
High-speed system
cloc
k oscillator
Inter
nal b
us
XT1/P123
XT2/EXCLKS
/P124
f
SUB
f
CLK
CSS
CLS
OSTS1
OSTS0
OSTS2
3
MOST
18
MOST
17
MOST
15
MOST
13
MOST
11
MSTOP
EXCLK
OSCSEL
AMPH
f
MX
f
XT
X1/P121
X2/EXCLK
/P122
f
X
f
EX
MCM0
MCS
CPU
MOST
10
MOST
9
MOST
8
XTSTOP
HIOSTOP
OSCSELS
AMPHS0
AMPHS1
CLS
f
IH
f
MAIN
f
IL
f
EXS
EXCLKS
High-speed on-chip oscillator
trimming register(HIOTRM)
HIOTRM0
6
HIOTRM1
HIOTRM2
HIOTRM3
HIOTRM4
HIOTRM5
X1 oscillation
stabilization time counter
Nor
mal
oper
ation mode
HAL
T mode
ST
OP mode
Standb
y controller
Cr
ystal/cer
amic
oscillation
Subsystem cloc
k
oscillator
Exter
nal input
cloc
k
Exter
nal input
cloc
k
High-speed on-chip oscillator
IOscillation (4 MHz (TYP
.))
Oscillation (12 MHz (TYP
.))
Oscillation (24MHz (TYP
.))
Oscillation (8 MHz (TYP
.))
Oscillation (16 MHz (TYP
.))
Oscillation (32 MHz (TYP
.))
Cr
ystal
oscillation
Lo
w-speed
on-chip oscillator
Oscillation (15 kHz (TYP
.))
Main system cloc
k
source selector
Option b
yte (000C0H)
WDTON
WDSTBYON
HAL
T/ST
OP mode signal
W
atchdog timer
CPU cloc
k
and per
ipher
al
hardw
are
cloc
k source
selection
Cloc
k output/
b
uzz
er output
Ser
ial arr
a
y unit 0
Ser
ial arr
a
y unit 1
A/D con
v
er
ter
Ser
ial interf
ace IICA0
Inter
nal b
us
P
er
ipher
al enab
le
register 0 (PER0)
Cloc
k oper
ation
status control
register (CSC)
Cloc
k oper
ation mode
control register
(CMC)
Controller
Option b
yte (000C2H)
FRQSEL0 to FRQSEL3
High-speed system
cloc
k oscillator
Oscillation (1 MHz (TYP
.))
Selector
Controller
Real-time cloc
k,
12-bit Inter
v
al timer
Timer arr
a
y unit 0
HOCODIV2
HOCODIV1
HOCODIV0
High-speed on-chip
oscillator frequency select
register (HOCODIV)
SAU0
EN
SAU1
EN
IICA0
EN
ADC
EN
RTC
EN
TAU0
EN
WUTMMCK0
RTCLPC
Subsystem clock supply
mode control register
(OSMC)
Selector
Controller
WUTMMCK0
Oscillation (6 MHz (TYP
.))
IOscillation (3 MHz (TYP
.))
IOscillation (2 MHz (TYP
.))
(Rema
rk
is list
ed on the
next pag
e after next
.)
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