Renesas rl78 Manuel D’Utilisation

 

RL78/G1A 

 

CHAPTER  11   A/D  CONVERTER 

R01UH0305EJ0200  Rev.2.00 

 

 

391  

Jul 04, 2013 

If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison 

function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request 

signal (INTAD) is generated. 

 

•  While in the select mode 

When A/D conversion ends and an A/D conversion end interrupt request signal (INTAD) is generated, the A/D 

converter returns to normal operation mode from SNOOZE mode.  At this time, be sure to clear bit 2 (AWC = 0: 

SNOOZE mode release) of the A/D converter mode register 2 (ADM2).  If the AWC bit is left set to 1, A/D 

conversion will not start normally in the subsequent SNOOZE or normal operation mode. 

 

• While in the scan mode 

If even one A/D conversion end interrupt request signal (INTAD) is generated during A/D conversion of the four 

channels, the clock request signal remains at the high level, and the A/D converter switches from the SNOOZE 

mode to the normal operation mode.  At this time, be sure to clear bit 2 (AWC = 0: SNOOZE mode release) of A/D 

converter mode register 2 (ADM2) to 0.  If the AWC bit is left set to 1, A/D conversion will not start normally in the 

subsequent SNOOZE or normal operation mode. 

 

 

ADCS

Interrupt signal

(INTAD)

INTRTC

Clock request signal

(internal signal)

Conversion

channels

Channel 

1

Channel 

2

Channel 

3

Channel 

4

An interrupt is generated 

when conversion on one 

of the channels ends.

The clock request signal 
remains at the high level.

Clearing AWC bit to 0