Hynix HMP125U6EFR8C-S6 Fascicule

Rev. 0.3 / Nov. 2008                                                                                                                                                                           19

Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met 

with all combinations of EMRS bits 10 and 11.

5. Definitions for IDD
 

LOW is defined as Vin

 ≤ VILAC (max)

 

HIGH is defined as Vin

 ≥ VIHAC (min)

STABLE is defined as inputs stable at a HIGH or LOW level

 

FLOATING is defined as inputs at VREF = VDDQ/2

 

SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control sig-   

       nals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not     
       including masks or strobes.

Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin 
(IDD);CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus 
inputs are SWITCHING

mA

Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = 
tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin (IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between 
valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W

mA

Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address 
bus inputs are STABLE; Data bus inputs are FLOATING

mA

Precharge quiet standby current; All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control 
and address bus inputs are STABLE; Data bus inputs are FLOATING

mA

Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and 
address bus inputs are SWITCHING; Data bus inputs are SWITCHING

mA

Active power-down current; All banks open; tCK = tCK(IDD); 
CKE is LOW; Other control and address bus inputs are STABLE; 
Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

mA

Slow PDN Exit MRS(12) = 1

mA

Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP =tRP(IDD); CKE is 
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data 
bus inputs are SWITCHING

mA

Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK 

= tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; 
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

mA

Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), 

AL = 0; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid 
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W

mA

Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is 
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are 
SWITCHING

mA

Self refresh current; CK and CK at 0V; CKE 

≤ 0.2V; Other control and 

address bus inputs are FLOATING; Data bus inputs are FLOATING. 
IDD6 current values are guaranted up to Tcase of 85℃ max.

Normal

mA

Low Power

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), 

AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE 
is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data 
pattern is same as IDD4R; - Refer to the following page for detailed timing conditions 

mA