Hynix HMP125U6EFR8C-S6 Fascicule

Rev. 0.3 / Nov. 2008                                                                                                                                                                           3

CK[2:0], CK[2:0]

SSTL

Differential 

Crossing

CK and /CK are differential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sam-

pled on the crossing of positive edge of CK and negative edge of /CK. Output (read) data 

is reference to the crossing of CK and /CK (Both directions of crossing)

CKE[1:0]

SSTL

Active High

Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when 

low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self 

Refresh mode.

S[1:0]

SSTL

Active Low

Enables the associated DDR2 SDRAM command decoder when low and disables the 

command decoder when high. When the command decoder is disabled, new commands 

are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is 

selected by S1

RAS, CAS, 

WE

SSTL

Active Low

/RAS,/CAS and /WE(ALONG WITH S) define the command being entered.

ODT[1:0]

SSTL

Active High

Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 

SDRAM mode register.

Vref

Supply

Reference voltage for SSTL18 inputs

V

DDQ

Supply

Power supplies for the DDR2 SDRAM output buffers to provide improved noise immu-

nity. For all current DDR2 unbuffered DIMM designs, V

DDQ

 shares the same power plane 

as V

DD

 pins.

BA[2:0]

SSTL

-

Selects which DDR2 SDRAM internal bank of four or eight is activated.

A[9:0], A10/AP, 
A[13:11]

SSTL

-

During a Bank Activate command cycle, Address input difines the row 

address(RA0~RA15)

During a Read or Write command cycle, Address input defines the column address when 

sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to 

the column address, AP is used to invoke autoprecharge operation at the end of the 

burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines 

the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge 

command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to 

precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn 

inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.

DQ[63:0],

CB[7:0]

SSTL

-

Data and Check Bit Input/Output pins.

DM[8:0]

SSTL

Active High

DM is an input mask signal for write data. Input data is masked when DM is sampled 

High coincident with that input data during a write access. DM is sampled on both edges 

of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS 

loading.

V

DD

,V

SS

Supply

Power and ground for the DDR2 SDRAM input buffers, and core logic. V

DD

 and V

DDQ

 

pins are tied to V

DD

/V

DDQ

 planes on these modules.

DQS[8:0],

DQS[8:0]

SSTL

Differential 

crossing

Data strobe for input and output data. For Rawcards using x16 organized DRAMs, 

DQ0~7 connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin of 

the DRAM

SA[2:0]

-

These signals are tied at the system planar to either V

SS

 or V

DD

 to configure the serial 

SPD EEPROM.

SDA

-

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A 

resister must be connected to V

DD

 to act as a pull up.

SCL

-

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be 

connected from SCL to V

DD

 to act as a pull up on the system board.

VDDSPD

Supply

Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power 

plane. EEPROM supply is operable from 1.7V to 3.6V.