Hynix HMP125U6EFR8C-S6 Manuel D’Utilisation
3
DDR2 Device Operations & Timing Diagram
Self
Idle
Setting
EMR
Bank
Precharging
Power
Writing
ACT
RDA
Read
SRF
REF
CKEL
(E)MR
CKEH
CKEH
CKEL
Write
Automatic Sequence
Command Sequence
RDA
WRA
Read
PR, PRA
PR
Refreshing
Refreshing
Down
Power
Down
Active
with
RDA
Reading
with
WRA
Active
Precharge
Reading
Writing
PR(A) = Precharge (All)
(E)MR = (Extended) Mode Register
SRF = Enter Self Refresh
REF = Refresh
(E)MR = (Extended) Mode Register
SRF = Enter Self Refresh
REF = Refresh
CKEL = CKE LOW, enter Power Down
CKEH = CKE HIGH, exit Power Down, exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
CKEH = CKE HIGH, exit Power Down, exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
Note: Use caution with this diagram. It is intended to provide a floorplan of the possible state transitions
1.1 Simplified State Diagram
All banks
precharged
Activating
CKEH
Read
Write
CKEL
MR
CKEL
Sequence
Initialization
OCD
calibration
CKEL
CKEL
CKEL
Autoprecharge
Autoprecharge
PR, PRA
PR, PRA
and the commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions,
enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions,
1. Functional Description
- among other things - are not captured in full detail
WRA
Write
Figure 1. DDR2 SDRAM simplified state diagram