Intel N455 AU80610006237AA Manuel D’Utilisation
Codes de produits
AU80610006237AA
Datasheet
15
Signal Description
2.1
Processor Legacy Signals
Table 2-3. Processor Legacy Signals
Signal Name
Description
Direction
Type
A20M#
If A20M# (Address-20 Mask) is asserted, the
processor masks physical address bit-20 (A20#)
before looking up a line in any internal cache and
before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1-MB boundary.
Assertion of A20M# is only supported in real mode.
processor masks physical address bit-20 (A20#)
before looking up a line in any internal cache and
before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1-MB boundary.
Assertion of A20M# is only supported in real mode.
I
Core
CMOS
BSEL[2:0]
BSEL[2:0] (Bus Select) are used to select the
processor input clock frequency.
processor input clock frequency.
O
Core
CMOS
CPUPWRGOOD
CPUPWRGOOD (Power Good) is a processor input.
The processor requires this signal to be a clean
indication that the clocks and power supplies are
stable and within their specifications. ‘Clean’ implies
that the signal will remain low (capable of sinking
leakage current), without glitches, from the time
that the power supplies are turned on until they
come within specification. The signal must then
transition monotonically to a high state.
CPUPWRGOOD can be driven inactive at any time,
but clocks and power must again be stable before a
subsequent rising edge of CPUPWRGOOD. It must
also meet the minimum pulse width specification.
The CPUPWRGOOD signal must be supplied to the
processor; it is used to protect internal circuits
against voltage sequencing issues. It should be
driven high throughout boundary scan operation.
The processor requires this signal to be a clean
indication that the clocks and power supplies are
stable and within their specifications. ‘Clean’ implies
that the signal will remain low (capable of sinking
leakage current), without glitches, from the time
that the power supplies are turned on until they
come within specification. The signal must then
transition monotonically to a high state.
CPUPWRGOOD can be driven inactive at any time,
but clocks and power must again be stable before a
subsequent rising edge of CPUPWRGOOD. It must
also meet the minimum pulse width specification.
The CPUPWRGOOD signal must be supplied to the
processor; it is used to protect internal circuits
against voltage sequencing issues. It should be
driven high throughout boundary scan operation.
I
Core
CMOS
DPRSTP#
DPRSTP#, when asserted on the platform causes the
processor to transition from the Deep Sleep State to
the Deeper Sleep state. In order to return to the
Deep Sleep State, DPRSTP# must be deasserted.
DPRSTP# is driven by the chipset.
processor to transition from the Deep Sleep State to
the Deeper Sleep state. In order to return to the
Deep Sleep State, DPRSTP# must be deasserted.
DPRSTP# is driven by the chipset.
I
Core
CMOS
DPSLP#
DPRSLP#, when asserted on the platform causes the
processor to transition from the Sleep State to the
Deep Sleep state. In order to return to the Sleep
State, DPSLP# must be deasserted. DPRSTP# is
driven by the chipset.
processor to transition from the Sleep State to the
Deep Sleep state. In order to return to the Sleep
State, DPSLP# must be deasserted. DPRSTP# is
driven by the chipset.
I
Core
CMOS
EXTBGREF
External Bandgap Reference.
I
Core
Analog