Samsung 100737108-A Manuel D’Utilisation
Spinpoint M8-DVR OEM Product Manual REV 1.0
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DATA CHARACTER-A data character is a combination of a byte value with the control variable equal to D.
DWORD-A Dword is thirty-two (32) bits of data. A Dword may be represented as 32 bits, as two adjacent
words, or as four adjacent bytes. When shown as bits the least significant bit is bit 0 and most significant bit is
bit 31. The most significant bit is shown on the left. When shown as words the least significant word (lower)
is word 0 and the most significant (upper) word is word 1. When shown as bytes the least significant byte is
byte 0 and the most significant byte is byte 3.
words, or as four adjacent bytes. When shown as bits the least significant bit is bit 0 and most significant bit is
bit 31. The most significant bit is shown on the left. When shown as words the least significant word (lower)
is word 0 and the most significant (upper) word is word 1. When shown as bytes the least significant byte is
byte 0 and the most significant byte is byte 3.
DWORD SYNCHRINIZATION-The state in which a receiver has recognized the comma sequence and is
producing an aligned data stream of Dwords (four contiguous bytes) from the zero-reference of the comma
character.
producing an aligned data stream of Dwords (four contiguous bytes) from the zero-reference of the comma
character.
ENCODED CHARACTER-An encoded character is the output of the 8b/10b encoder – the result of
encoding a character. An encoded character consists of 10 bits, where bit 0 is the most significant bit and bit
9 is the least significant. The bits in an encoded character are symbolically referred to as “abcdeifghj” where
encoding a character. An encoded character consists of 10 bits, where bit 0 is the most significant bit and bit
9 is the least significant. The bits in an encoded character are symbolically referred to as “abcdeifghj” where
“a” corresponds to bit 0 and “j” corresponds to bit 9.
ELASTICITY BUFFER-The elasticity buffer is a portion of the receiver where character slipping and/or
character alignment is performed.
character alignment is performed.
FIRST PARTY DMA ACCESS -First-party DMA access is a method by which a device accesses host
memory.
memory.
FIRST PARTY DMA MODE (FPDMA) - A device which is operating in First-party DMA mode uses First-
party DMA as a primary communications method between the host and the device. A software driver uses
legacy mode commands to place the device into First-party DMA mode of operation. The legacy-mode
command places the device into the First-party DMA mode of operation and the command protocol used between
a device and host when in First-party DMA mode are not specified by this specification.
party DMA as a primary communications method between the host and the device. A software driver uses
legacy mode commands to place the device into First-party DMA mode of operation. The legacy-mode
command places the device into the First-party DMA mode of operation and the command protocol used between
a device and host when in First-party DMA mode are not specified by this specification.
FIRST DATA PHASE- The FPDMA Data Phase is the period from the reception of a DMA Setup FIS until
either the exhaustion of the associated data transfer count or the assertion of the ERR bit in the shadow Status
register.
either the exhaustion of the associated data transfer count or the assertion of the ERR bit in the shadow Status
register.
FIS-Stands for Frame Information Structure.
FRAME UNFIORMATION STRUCTURE-The user payload of a frame, does not include the SOF, CRC,
and EOF delimiters.
and EOF delimiters.
Frame-A frame is an indivisible unit of information exchanged between a host and device. A frame consists
of a SOF primitive, a Frame Information Structure, a CRC calculated over the contents of the FIS, and an
EOF primitive-
of a SOF primitive, a Frame Information Structure, a CRC calculated over the contents of the FIS, and an
EOF primitive-
LEGACY M ODE -Legacy m o d e is the mode of operation w h i c h provides s o f tw a r e -transparent
communication of commands and status between a host and device using the ATA Command Block and
Control Block registers.
communication of commands and status between a host and device using the ATA Command Block and
Control Block registers.
LEGAL CHARACTER-Legal character is one for which there exists a valid decoding, either into the data
character or control character fields. Due to running disparity constraints not all 10-bit combinations result in a
legal character. Additional usage restrictions in Serial ATA result in a further reduction in the SATA
defined control character space.
character or control character fields. Due to running disparity constraints not all 10-bit combinations result in a
legal character. Additional usage restrictions in Serial ATA result in a further reduction in the SATA
defined control character space.
OOB SIGNAL DETECTOR-This block decodes Out of Band signal from the high speed input signal path.