Cypress CY7C1248V18 Manuel D’Utilisation
CY7C1246V18, CY7C1257V18
CY7C1248V18, CY7C1250V18
CY7C1248V18, CY7C1250V18
Document Number: 001-06348 Rev. *D
Page 2 of 27
Logic Block Diagram (CY7C1246V18)
Logic Block Diagram (CY7C1257V18)
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
R
ead Add. Decode
Read Data Reg.
R/W
DQ
[7:0]
Output
Logic
Reg.
Reg.
Reg.
8
8
16
8
NWS
[1:0]
V
REF
W
rite Add. Decode
8
8
LD
Control
21
2M x 8 A
rray
2M x 8 Arra
y
Write
Reg
Reg
Write
Reg
Reg
CQ
CQ
R/W
DOFF
QVLD
8
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. De
code
Read Data Reg.
R/W
DQ
[8:0]
Output
Logic
Reg.
Reg.
Reg.
9
9
18
9
BWS
[0]
V
REF
W
rite Add. De
code
9
9
LD
Control
21
2M x 9
Array
2M x 9 Arr
a
y
Write
Reg
Reg
Write
Reg
Reg
CQ
CQ
R/W
DOFF
QVLD
9