Seagate ST940811A Manuel D’Utilisation

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Momentus 5400 FDE Product Manual, Rev. C

The Momentus 5400 FDE is consistent with the ATA Interface implementation of the Momentus 5400.2 prod-
ucts with the known exceptions listed within this section (Section 4.1.1 subordinate sections).

If multi-word DMA model is selected, the drive response is indeterminate, and the ATA bus will hang. Due to 
this limitation, the drive will violate the DCO Set requirement in the ATA specification.

Interrupts disabled mode is entered upon setting of the nIEN bit to 1, in the Device Control Register as shown 
in the ATA Specification.    

Upon entry of this mode the drive will behave normally in the absence of issuance of the following user data 
access commands, to the drive:

• READ/WRITE BUFFER

• READ/WRITE SECTOR

• READ/WRITE SECTOR EXT

• READ/WRITE MULTIPLE

• READ/WRITE MULTIPLE EXT

• READ/WRITE DMA

• READ/WRITE DMA EXT

If any of the identified data access commands are issued to the drive, the drive will tri-state the data bus and 
the retrieved data will be indeterminate. Additionally, the drive will return indeterminate values in the status reg-
ister.

Upon entry into the described state, the drive will remain in this state until you power cycle the drive.

If the nIEN bit is set to 1 and none of the identified data access commands are issued, the nIEN bit may be 
returned to 0 and the drive will continue with normal operation in the Interrupts Enabled mode.

In the Interrupts Enabled mode, the drive has limited support for the host to check the status register of the 
drive while waiting for the data transfer interrupt.

If the host polls the status register, while waiting for interrupts and the drive has not yet posted the interrupt, the 
drive will tri-state the data bus. This limitation is only an issue for any host that might choose to transfer the 
data prior to the DRQ bit being set. For instance, any host that reads a status of 0x20 may, based on the drive 
Busy bit and Error bit being cleared, choose to transfer the data, even though the DRQ bit is not set. This is not 
recommended host behavior, and, if implemented, would result in undesirable results.

This limitation is not an issue for hosts that simply wait for the interrupt to be posted.

This is not believed to be an issue for hosts that check status but wait for the DRQ bit to be set.

HOB

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