Epson RTC-72421 A Manuel D’Utilisation
RTC - 72421 / 72423
Page - 16
MQ - 162 - 03
2. Read/write of S1 to W registers
Use one of the procedures shown below to access registers other than the control registers (CD, CE, and CF) while the RTC is
operating. Note that the control registers can be accessed regardless of the status of the BUSY bit.
Read or write when the HOLD bit is used
From previous process
To next process
Read the BUSY bit
BUSY bit = 0?
W ait 190
µ
s
NO
YES
Read required digit data or
set the time
HOLD bit
←
1
HOLD bit
←
0
HOLD bit
←
0
or
From previous process
To next process
Read the BUSY bit
BUSY bit = 0?
NO
YES
Read requierd digit data or
set the time
HOLD bit
←
1
HOLD bit
←
0
HOLD bit
←
0
Read when the HOLD bit is not used
From previous process
To next process
Store the read data (A
←
data)
A=B?
NO
YES
Read the required digit data
(1st time)
Read the required digit data
(2nd time)
Store the read data (B
←
data)
The operation when the HOLD bit is not used involves reading the same digit twice and comparing the read values. This is to
avoid the problem of reading unstable data that would occur if the data was read while the RTC was incrementing the count.
3. Write to 30-second ADJ bit
The 30-seconds ADJ function is enabled by writing 1 to the 30-seconds ADJ bit. Note that the counter registers (S1 to W) cannot be
accessed for 76.3
accessed for 76.3
µ
s after this write. Therefore, follow one of the procedures shown below to use this function.
START
END
30 s ADJ bit
←
1
Read the 30 s ADJ bit
Wait 76.3
µ
s
NO
YES
30 s ADJ bit=0?
or
START
END
30 s ADJ bit
←
1
Read the 30 s ADJ bit
NO
YES
30 s ADJ bit=0?
Note
The crystal unit could be damaged if subjected to excessive shock. If the crystal unit should stop operating for such a reason, the
timer within the RTC will stop. While the crystal unit is operating, the BUSY bit is automatically reset every 190
µ
s and the 30-
seconds ADJ bit, every 76.3
µ
s , but this automatic reset cannot be done if the oscillation stops. Therefore, in such a status, it is no
longer possible to escape from the BUSY bit status check loop shown in subsection 2 above or the 30-seconds ADJ bit status check
loop shown in subsection 3 above, and you should consider backing up the system. To design a fail-safe system, provide an escape
from the loop to a procedure that can process such an error if the loop is repeated for more than 0.5 ms to 1.0 ms.
loop shown in subsection 3 above, and you should consider backing up the system. To design a fail-safe system, provide an escape
from the loop to a procedure that can process such an error if the loop is repeated for more than 0.5 ms to 1.0 ms.