Nvidia 780I SLI Manuel D’Utilisation
780i 3-Way SLI Motherboard
NVIDIA Corporation
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October 17, 2007 | DU-03597-001_v01
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W to R Command Delay
The Write-to-Read (tWRD) command delay is the amount of cycles required
The Write-to-Read (tWRD) command delay is the amount of cycles required
between a valid write command and the next read command. A lower cycle
time results in better performance but is can instability. Adjustable from 0 to
6 cycles.
time results in better performance but is can instability. Adjustable from 0 to
6 cycles.
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W to W Timing
The Write-to-Write (tWRWR) timing is the number of clock cycles between
the last write and the subsequent Write command to the same physical bank.
the last write and the subsequent Write command to the same physical bank.
Adjustable from 2 to 15 cycles.
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CAS Latency
The CAS Latency (tCL) is the time (in number of clock cycles) that elapses
The CAS Latency (tCL) is the time (in number of clock cycles) that elapses
after the memory controller sends a request to read a memory location and
before the data is sent to the module's output pins. The value shown cannot
be changed.
before the data is sent to the module's output pins. The value shown cannot
be changed.
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Clock Drive Strength
This value is filled in by the system and can not be changed by the user.
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Command Per Clock
The Command Per Clock (tCPC) sets the Command Rate for the memory
The Command Per Clock (tCPC) sets the Command Rate for the memory
controller. The value shown cannot be changed
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Async Latency
This value is filled in by the system and can not be changed by the user.
This value is filled in by the system and can not be changed by the user.