Motorola SC140 Manuel D’Utilisation
12
Using the SC140 Enhanced OnCE Stopwatch Timer
Figure 7. Event Counter Dialog Box When Debugger Halts at Breakpoint
5
Setting Up the System Clock Speed
Every SC140-based device contains a Phase Lock Loop (PLL) block, which controls the operating
frequency of the device. The frequency of the device is governed by the frequency control bits in the PLL
control register, as defined in Equation 2.
frequency of the device. The frequency of the device is governed by the frequency control bits in the PLL
control register, as defined in Equation 2.
Eqn. 2
In this equation:
•
MFI (multiplication factor integer), MFN (multiplication factor numerator), MFD (multiplication
factor denominator), and PODF (post division factor) are defined in the PCTL1 register.
factor denominator), and PODF (post division factor) are defined in the PCTL1 register.
•
PDF (pre-division factor) is defined in the PCTL0 register.
•
Fext is external input frequency to the chip at the EXTAL pin.
•
Fdevice is the operating frequency of the device.
The range of values of these terms are describe in [1].
Figure 8 and Figure 9 on page -13 illustrate the PLL control registers; PCTL0 and PCTL1, respectively.
Fdevice
Fext
MFI
MFN
MFD
MFD
-------------
+
×
PODF
PDF
×
-------------------------------------------------------
=