Cypress CY7C65113C Manuel D’Utilisation

Document #: 38-08002  Rev. *D

Page 34 of 49

Bit 3: Bus Activity.

This is a “sticky” bit that indicates if any non-idle USB event has occurred on the upstream USB port. Firmware should 

check and clear this bit periodically to detect any loss of bus activity. Writing a ‘0’ to the Bus Activity bit clears it, while writing 

a ‘1’ preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it.

Bits 4 and 5: D– Upstream and D+ Upstream.

These bits give the state of each upstream port pin individually: 1 = HIGH, 0 = LOW.

Bit 6: Endpoint Mode.

This bit used to configure the number of USB endpoints. See Section 17.2 for a detailed description.

Bit 7: Endpoint Size.

This bit used to configure the number of USB endpoints. See Section 17.2 for a detailed description.

The hub generates an EOP at EOF1 in accordance with the USB 1.1 Specification, Section 11.2.2 as well as USB 2.0 specification

(section 11.2.5, page 304).

The CY7C65113C SIE supports operation as a single device or a compound device. This section describes the two device

addresses, the configurable endpoints, and the endpoint function.

The USB Controller provides two USB Device Address Registers: A (addressed at 0x10)and B (addressed at 0x40). Upon reset

and under default conditions, Device A has three endpoints and Device B has two endpoints. The USB Device Address Register

contents are cleared during a reset, setting the USB device addresses to zero and disabling these addresses. Figure 17-1 shows

the format of the USB Address Registers.

Bits[6..0]: Device Address.

Firmware writes this bits during the USB enumeration process to the non-zero address assigned by the USB host. 

Bit 7: Device Address Enable.

Must be set by firmware before the SIE can respond to USB traffic to the Device Address.

The CY7C65113C controller supports up to two addresses and five endpoints for communication with the host. The configuration

of these endpoints, and associated FIFOs, is controlled by bits [7,6] of the USB Status and Control Register (Figure 16-10). Bit

7 controls the size of the endpoints and bit 6 controls the number of addresses. These configuration options are detailed in

Table 17-1. Endpoint FIFOs are part of user RAM (as shown in Section 5.4.1).

000

Not Forcing (SIE Controls Driver)

001

Force D+[0] HIGH, D–[0] LOW

010

Force D+[0] LOW, D–[0] HIGH

011

Force SE0; D+[0] LOW, D–[0] LOW

100

Force D+[0] LOW, D–[0] LOW

101

Force D+[0] HiZ, D–[0] LOW

110

Force D+[0] LOW, D–[0] HiZ

111

Force D+[0] HiZ, D–[0] HiZ

Bit  #

7

6

5

4

3

2

1

0

Bit Name

Device 

Address 

Enable

Device 

Address 

Bit 6

Device 

Address 

Bit 5

Device 

Address 

Bit 4

Device 

Address 

Bit 3

Device 

Address 

Bit 2

Device 

Address 

Bit 1

Device 

Address 

Bit 0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0